linearity and limit our design performance in a real implementation. Hence, our goal for this project will be to achieve a resolution of at least 10 ps.
TECH ARTICLE
dependent on the matrix structure. Again, an approximate figure for the acquisition time can be computed as:
4.2. Area The number of delay stages (in both x and y axes) is, without a doubt, the main issue in this design, as it will determine to a great extent the circuit area and the power consumption. Indeed, increasing the number of stages will generate a larger number of dummy devices within the matrix which will consume power and waste area. On the other hand, if we were to consider the capacitive load which each delay stage has to handle, a square matrix structure will give us the same capacitive load in both x and y axes, thus being able to control the propagation delay difference by just sizing the delay elements in the right way.
Concluded in Part 2
REFERENCES [1] Vercesi, L., Liscidini, A., Castello, R., “Two-Dimensions Vernier Time-to-Digital Converter”, IEEE Journal of SolidState Circuits, August 2010, pp 1504-1512. [2] Chen, P., Liu, S. I., Wu, J., “A CMOS pulse shrinking delay element for time interval measurement”, IEEE Transactions on Circuits and Systems II,: Analog and Digital Signal Processing, September 2000.
In addition to those considerations, we must take into account the area consumed by the 5-bit encoding logic which will provide the system output, which can be considered as constant.
[3] Staszewski, R. B., Vemulapalli, S., Vallur, P., Wallberg, J., Balsara, P. T., “1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, March 2006.
Therefore, there must be a compromise between keeping the matrix as small as possible and making the rowcolumn ratio closer to 1, making area estimates totally dependent on the final matrix structure. For a general Vernier matrix (m rows and n columns), an approximate area estimate will be:
[4] Henzler, S., Koeppe, S., Lorenz, D., Kamp, W., Kuenemund, R., Schmitt-Landsiedel, D., “A Local Passive Time Interpolation Concept for Variation-Tolerant HighResolution Time-to-Digital Conversion”, IEEE Journal of Solid State Circuits, July 2008.
4.3. Power Supply voltage can be reduced to decrease the circuit power consumption without affecting its resolution. However, this will have a negative impact on the sampling rate since the overall propagation delay will be increased. By looking at the delay simulation results, a supply voltage of 0.8 V seems a reasonable choice.
[5] Rabaey, J. M., Chandrakasan, A., Nikolic,B., “Digital Integrated Circuits, a Design Perspective” 2nd edition, Prentice Hall, 2006.
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4.4. Sampling rate The sampling rate will depend mainly on both the number of delay stages and the total delay introduced by these stages for the worst case scenario. Hence, even if the absolute gate delay is not an important issue for the TDC resolution, it must be bounded by the accumulated delay of the longest delay line. Besides, by now we are neglecting the propagation delay introduced by the matrix latches and the 5-bit encoding stage. Again this figure is mainly Visit www.eeweb.com
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