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determined entirely by the delay element propagation delay within the chain. However, by using a Vernier delay line based architecture, the absolute propagation delay is no longer an issue since the resolution is a differential measure between two different delays, only limiting the TDC acquisition time. Taking into account these two criteria and after doing some literature survey, we finally found out one architecture which met both requirements. The solution proposed in [1] introduces a novel Vernier delay line TDC architecture which manages to reduce significantly the number delay stages for a given number of bits. The rationale behind this solution realizes that in a regular Vernier delay line only computes the time difference between elements located in the same position, thus achieving a linear delay function. However, the paper states that if time difference measurements between different delay elements were allowed the number of measurements would increase dramatically, yielding a wider time dynamic range. In particular, for an N step TDC, the number of delay stages is proportional to √(“N”), instead of N. All these time differences can be plotted into a, so called, Vernier plane, as shown in Figure 5. As can be seen, only a fraction of this plane is useful, i.e., has a linear and uniform succession of time differences which can be used. Therefore, latches will be placed in those plane dots to detect the point where the two signals meet, thus giving a readout in thermo-code format. Besides, there are plane points which do not contribute to the time dynamic range, thereby they are not used and -4∆
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can be neglected. However, due to a simpler and more homogeneous design in the delay elements, these points are usually connected to the delay line thus acting as dummy load capacitances. In this sense, S-R latches are preferred over D flip-flops since they have a symmetric structure which will also help delay homogeneity in both the paths. Finally, as has been done in the paper where this solution is proposed, we will limit our design space to delay lines whose elements are compliant with the following relationships:
Under this assumption, any point in the Vernier plane can be expressed as:
Moreover, as the useful values of y(i) are limited to the range [0,k], the above equation can be inverted, yielding the following relationships:
4. PERFORMANCE ESTIMATION Before discussing our design, we would like to present some performance estimations covering the main design parameters. They are based on the prior analysis of both the simulation models used for this 8∆ 12∆ project and the chosen architecture features. Besides, for the following estimations, we are assuming that both 11∆ 15∆ START and STOP signals will remain active for the whole acquisition time. 14∆
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Figure 5: 2-D Vernier plane for τ1=4Δ and τ2=3Δ
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4.1. Resolution From the previous discussion, it may seem that with this Vernier architecture we can go for a really high resolution. However, we are aware that this approach is not realistic, since we are not considering at this level several design parameters such as interconnection delay, manufacturing mismatch and noise, which will degrade the circuit