number of delay elements. Because of both area and power consumption increases, while the sampling rate is reduced since the reference signal has an additional propagation time through its delay chain. td1
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td1
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3.1.4. Local passive time interpolation The last considered TDC architecture is presented in [4], which achieves sub-gate delay resolution by time interpolation between two signals delayed by one inverter propagation delay, as seen in Figure 4. Using this approach, a new set of signals between the two signals mentioned before, can be defined as: interpolated signals
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VB
td2
relevant voltage range for comparator
Figure 2: Vernier delay line architecture [4] VA
3.1.3. Pulse shrinking The two previous approaches were based on the delay elements propagation time to compute the desired time measurement. However, this is not the only possible solution. The TDC solution proposed in [2], use the structure showed in Figure 3, where the target signal loops for a given time. Delay Line Total k stage
counter Vin
RESET
Tin
Tr
1
1
Ă&#x;
1
1
Vout
output pulse
Figure 3: Pulse shrinking TDC architecture [2]
Within this structure, the target signal width is iteratively reduced due to the different gate sizing, until it disappears. The reduction rate is given by the following expression:
Finally, a counter will store the number of iterations within the loop which is related to the target signal width. The main advantage of this architecture is clearly the reduced area needed for a given resolution. In fact, the delay elements can be set independently of the required dynamic range. However, a high resolution TDC based on this approach demands a slow width reduction, hence decreasing the acquisition rate.
Tinv
Figure 4: Time interpolation example [4]
Therefore, by just using a simple resistive divider between Vin and Vd, we can obtain several uniformly distributed signals between them, increasing the system resolution. The complete system will be composed of several coarse grain delay stages in a differential delay line configuration along with resistors which will provide the fine grain time measurement by means of time interpolation. 3.2. 2-D Vernier delay line Looking at all the different available TDC architectures described above, all of them have several benefits and drawbacks, making the selection a tough task. However, we focused on several features which we considered the most relevant ones, thus helping us to choose our final design architecture. One particular characteristic which seems to be common to most of the approaches is the number of delay stages needed to achieve a certain time dynamic range, i.e., growing in an exponential fashion with the readout number of bits. This feature limits in practice the TDC linearity due to delay element manufacturing mismatch and makes it very sensitive to phase noise, thus limiting its final resolution. Therefore, the number of delay stages became one of the main criteria in order to select a specific TDC architecture. Another issue that we were worried about is the minimum delay introduced by the delay elements themselves. Some TDC architectures rely on the fact that the resolution is Visit www.eeweb.com
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