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1. INTRODUCTION
• Area (computed as the sum of the transistor widths)
Nowadays, many systems use time measurements as part of their calculations to perform a certain functionality. However, very often, these measurements are not required to be very accurate and a millisecond or microsecond resolution is enough. Time-to-digital converters (TDCs) are devices which can be used when more resolution is required. They can accurately measure the time difference between two events, usually achieving a resolution within the picoseconds scale. Their applications range from high energy physics and astronomy instrumentation to RF synthesizers and medical equipment.
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Although there are different ways to perform this operation, their basic principle consists of a signal going through several delay elements (typically CMOS inverters), which provide the system time quantization. Hence, as if it were an ADC, a digital code is generated depending on how far the signal has gone. 1.1. AIM OF THIS ARTICLE As can be inferred from the previous section, CMOS technology has become the most popular way to implement these high precision time measurement devices. This document presents the analysis and design details of a TDC architecture using the 80 nm CMOS technology. This article serves as an overview for various architecture and analysis of the chosen architecture which will be presented. Thorough analysis of the scheme followed by transistor level design results would be presented.
2. DESIGN SPECIFICATIONS As mentioned in the introductory section, the proposed project targets to design of a time-to digital converter using the 80 nm CMOS technology. This design has to meet the following minimum requirements to be considered as a valid solution: • Minimum resolution: 40 picoseconds • Number of stages: 32 (5-bit binary readout) • Minimum transistor size: Lmin=80 nm, Wmin=120 nm The design will be carried out at the transistor level, i.e., not taking into account the circuit layout. Any other parameter which is not present in the requirements above mentioned is free to choose. The metrics used to determine the quality of the design will be the following: • Speed (time resolution)
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• Sampling rate (number of acquisitions per second)
3. PROPOSED TDC ARCHITECTURE Once the project goals have been described, the next step will consist of selecting one among all the available CMOS based TDC architectures. 3.1. State of the art TDCs
3.1.1. Single delay line In this TDC architecture [3], the target signal propagates through a delay element chain, each delay element output being connected to a latch. A reference signal triggers the latches, sampling the delay chain state. The value stored within the latches indicates how far the target signal has propagated through the delay chain, hence providing an accurate time measurement in a pseudo thermo-code format. START
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Figure 1: Single delay line TDC architecture
This is the simplest CMOS based TDC architecture, due to the fact that it uses very simple elements such as delay elements and latches. However, its resolution is in direct relationship with the delay elements propagation time, giving typically a lower resolution when compared with other techniques.
3.1.2. Vernier delay line The Vernier delay line TDC is a variation of the previous architecture. In this solution, additional delay elements are added to the reference signal which triggers the latches. These new delay elements have a slightly smaller propagation delay than the ones within the target signal path, causing the reference signal to propagate faster than the target signal and, therefore, providing a resolution which is equal to the difference between the delay elements propagation time. With respect to the previous solution, due to a differential time measurement this approach will need twice the
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