Modern Printed Circuits: Cadence by EEWeb Magazines

DECEMBER 1 â&#x20AC;&#x2DC;13

Hemant Shah, Cadence

3D Design Strategies

Josh Moore, Cadence

LED Circuit Design

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CONTENTS

Modern Printed Circuits

TECH ARTICLE

Critical Design Steps for A Third Design Choice LED PCBs Fig. 1

Whatever laminate is used, PTFE or otherwise, the copper remaining after etch must be cleaned or automated optical inspection to detect trace shorts or opens will be unreliable and soldermask will not stick. The best way to clean the copper is an abrasive scrub. However, all the suppliers of PTFEbased laminates advise that the laminate surface fresh from copper etch is best for adhesion and is compromised by scrubbing. There are alternative cleaning methods, though none are as satisfactory as scrubbing to support AOI of the copper and soldermask adhesion. Consequently, the copper is scrubbed before inspection. A plasma process is used after the scrubbing to reinvigorate the exposed laminate, to return the “tooth” to the surface so that soldermask will adhere, if it is an outside layer, or to aid subsequent lamination. However, the plasma oxidizes the copper, so it must be cleaned again if soldermask is to be applied. To avoid compromising the PTFE laminate surface by another scrubbing, a chemical clean for the copper follows in lieu of scrubbing, in preparation for soldermask. The panel must be dried immediately to eliminate moisture that could stain the copper and thereby inhibit soldermask adhesion. The process is a balancing act. Sometimes it does not work and the soldermask has to be stripped, the panel cleaned again and dried, and the soldermask reapplied. Instead of the standard practice of covering a board in soldermask (leaving openings for pads and so forth) rf and microwave designers commonly soldermask only the circuitry (except for the pads,etc) leaving the PTFE laminate surface open. The copper can be scrubbed, AOI can be performed successfully, the soldermask is applied to the copper where it sticks, and there is no need to worry about it on the laminate because it develops off. Another common approach is to restrict the deposit of soldermask to little dams next to pads, which limit solder from traveling down the traces (Figure 1). This approach may be easy to implement for simple circuits, but tedious if thousands of dams are required (Figure 2).

TECH ARTICLE

The need for scrubbing or chemical cleaning of the copper can be avoided altogether, and therefore the need to plasma treat the surface of the PTFE dielectric if a lamination will follow, if gold is plated over the copper before etch. The gold does not oxidize, remaining bright after etch, so does not require cleaning to be ready for AOI. Furthermore, a full soldermask with conventional solder openings can adhere to the board. Of course, gold is expensive, but one (or more) cleaning processes and a plasma process are eliminated. There is with gold the issue of copper migration to consider as well. Over time, copper and gold tend to diffuse into each other, the copper brought to the surface oxidizes, and contact resistance increases as a result of the oxidation. Higher temperatures accelerate the process. Nickel ordinarily is used as a barrier layer between copper and gold to prevent diffusion, however nickel cannot be used for rf and microwave circuits. At rf and microwave frequencies, the skin effect predominates in conductors: Most of the current flows in the outside of traces. Nickel is a lossy metal compared to copper especially at high frequencies, and the skin effect would tend to concentrate much of the current through the nickel near the trace surface. Copper diffusion into gold really is not a problem, unless the fabricated boards are kept in inventory a long time before assembly. Once components are soldered to their goldplated contacts, there is no worry about contact deterioration. Regarding the cost of gold, the plating amounts to a few microns thick. If there’s a plane on one side of the board, that would involve slightly more expense (more gold) than a signal layer, of course. Yet, there are fewer process steps with full-body plated gold. The copper is simply plated and then etched, with the gold as an etch resist, leaving the final metal surface finish. Yield ultimately governs the cost of fabrication.

If panels must be reprocessed because soldermask fails to adhere to blemished board traces, or worse if panels must be scrapped, cost accrues. For prototypes that are manufactured according to a flat price, that may not matter to designers. But as far as production quantities go, that is a different story.

Fig. 2

Design Choices for Soldermask on Microwave PCBs Soldermask dams surround pads on this microwave board, which was designed using Altium tools.

COVER INTERVIEW

This screen shot from the fab Genesis CAM tool reveals one of the soldermask dams. Biography Atar Mittal directs the design and assembly divisions of Sierra Circuits, a manufacturer of printed circuit boards in Sunnyvale, CA. He is responsible for the development of strategies and process automation tools for the fabrication and assembly of complex PCBs. Prior to Sierra Circuits, he held senior executive positions in R&D and technical marketing at computer hardware and software services companies in the United States and India. He holds a B.Tech. degree in Electrical Engineering from IIT Kharagpur (India), and a MS degree from CSU.

Hemant Shah: Dir. of Product Management of Allegro PCB Products at Cadence

COVER INTERVIEW Model

20 PCB Potential Gradie Josh Moore: Dir. of Product Marketing for OrCAD Solutions at Cadence

Using26SPICE

CIRCUIT PROJECT

Model PCB Potential Gradients Using SPICE

By David Cuthbert

EEWeb Contributing Author

In this article you’ll learn several techniques to control PCB Plane Po Gradients and you’ll learn how to simulate these techniques with You can then design successful low-level signal layouts on the first

PCB traces and planes offer electrical resistance to electrical c resulting in potential gradients and signal corruption. Voltage gra are especially important in low level analog circuitry—such as Ana Digital converters—where measurement accuracy can be compromi a potential gradient of just a few microvolts.

Modern Printed Circuits

650

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550

Careful Design Steps Criti

700 By

Zulki Khan President and Founder, Nexlogic Technologies

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TECH ARTICLE

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ical for

Although LEDs are steadily growing more popular in many applications, in recent years that growth has greatly and dramatically accelerated. This is due to the explosion of smartphones, iPods, and tablets, as well as other similar small and portable products for consumer, industrial, military, aerospace, and commercial markets. The ever shrinking liquid crystal display (LCD) displays used in these products now require white backlight versus the previously used standard green light. LEDs are quickly becoming the light of choice due to their shrinking size, as well as declining cost and longer life.

Modern Printed Circuits

High Voltage Drop On the other hand, LEDs pose a host of issues to the PCB layout designer, including thermal management challenges. The most prevalent is the fact that LEDs have a high voltage drop. Depending on the chipmaker, this can run between 3.1 to 4 volts, which is substantially large compared to the normal 1.08 or 2.7 volts. Hence, the PCB designer is looking at a huge voltage drop and they wonder how to incorporate it in his or her design. To maintain the white backlight compared to the earlier green light, battery voltage has to be increased. By increasing battery voltage, the size of the switching regulators is also increased, thus increasing the amount of needed circuitry. There are two ways of doing that; with the integrated LED circuitry, it can be placed close to the LED or separately.

Figure 1: MCPCB

The common practice today is to separate driver circuitry from the LED assembly to avoid the heat transfer from the LED assembly to the driver circuitry.

Design Considerations There are several key PCB design considerations involved here, but thermal management is foremost among them. Within thermal management, there are a few other key issues to ponder; those involve PCB material, thermal vias versus copper plate, and junction temperature. As far as PCB material, there is the traditional, cost-effective, widely available FR4 versus a metal core (MC) PCB. The biggest issue with FR4 is its poor thermal conductivity. On the other hand, a MCPCB, as shown in Fig. 1, is great thermal conductor, but it costs 20 to 30 percent more than FR4.

TECH ARTICLE Take for example a very bright power LED that is unable to use FR4 material. First, this particular LED and its level of power energy generate considerable heat. Second, FR4 doesn’t provide a direct thermal path from the junction of the LED’s base to the ambient. It has to use thermal vias or add copper plate. When copper plate is added, there is a slight chance it might short the LEDs if not connected properly. By using thermal vias, you are limiting the number of fab shops capable of making perfect thermal vias. In cases like these, the MCPCB is used because it effectively spreads the heat without encountering issues that the FR4 otherwise does. A more reliable technique for designing such an LED system is to design it with a controlled temperature rise for a given power dissipation. A way to do that is to use a controlling temperature resistor using a high thermal conductivity heat spreading material. Hence, an MCPCB and natural graphite, which is a heat spreader, are normally used for power LEDs. These two are proven to be thermally conductive materials that properly manage thermal flow and maintain temperature uniformity within the LED system. The third issue associated with thermal management is junction temperature, which is at the base of the LED. It’s highly important that it be properly measured. If it’s not, that junction temperature won’t be effectively dissipated. Moreover, if thermal management isn’t properly performed, then over time, poor thermal management will degrade the color at the output of an LED. Color and consistency of brightness will change, plus the LED will not last as long as it has been designed for. Another key consideration deals with coefficient of thermal expansion or CTE. There are thermal characteristics and impedance mismatches associated with various materials. It is critical that all materials being used are as closely CTE matched as possible. The reason is if an extremely high thermally conductive material comes in contact with a very low thermal conductive one, board delamination will result, as shown in Fig. 2.

Figure 2: Board De-lamination

Longer Life In addition to proper PCB designs and without question, OEMs producing smartphones, tablets, and other small and portable products want assurances of longer life for those LED-based backlights beyond the longer life specification LED suppliers promise on their datasheets. This is where PCB design expertise about thermal management and related issues kicks in to assure and extend those longer life specs that LED suppliers tout. This is especially valuable to OEMs producing those newer portable communications devices since the lifespan of their products is determined by the lifespan of those LEDs.

Modern Printed Circuits

Figure 3: Thermal Grease Compound So here, the common denominator in all LED-based PCBs is the importance of proper heat dissipation. For starters, heat that is not dissipated causes the P-N junction of the semiconductor needs to rise above the safe level, thus making the LED considerably more prone to failure. As a general rule of thumb that experienced LED-based PCB designers follow is in electronics systems, reliability and longevity are highly dependent on temperature. Temperature reductions as small as >5째C (>41째F) can double the service life of an electronic device. An associated design rule is to maintain a correct power supply to avoid overpowering LEDs. If an LED is overpowered, the temperature of the semiconductor layers rise above the safe level, thus the tendency for the device is to fail or malfunction and the lifespan of the device deteriorates.

TECH ARTICLE Also, it’s important to note that there is a variety of LED packaging for different types of LEDs, but here, the focus is on LEDs mainly used as backlight or status indicator light for multi-functional and thin profile portable applications such as smartphones, tablets, and other similar small products. Like in all other LED board applications, the heat sink plays a prominent role in thermal management. The PCB designer must select the correct heat sink for this small application. In cases like this, the proper heat sink may be a vertical heat sink with fins. Equally as important as designing in the right heat sink, the PCB designer must also connect that heat sink to a thermal pad, using thermal grease or compound as shown in Fig. 3. The thermal pad provides a path from the LED to the bare board and then to the heat sink. LED chip temperature is thus decreased and the device’s lifespan is extended. In some instances, inexperienced PCB designers aren’t aware of the importance of this thermal pad. Heat generated from such small packages, for example as small as 5/16-inch diameter, becomes a concern due to the increasing amount of current applied in such a miniscule area. Without a way to exhaust the heat—meaning if a thermal pad were not used, the life of the part would surely be short lived.

Via In Pad Via in pad technology is yet another tool the PCB designer can use to better manage the heat in an LED board design. It allows designers to utilize space more effectively when board real estate is critical. Typically, via in pad involves drilling a hole in the center of an SMT pad, filling it with a conductive or non-conductive material, and then plating over it to leave a flat surface so the hole is not visible. This allows the SMT part to be placed directly on top of the hole. If the hole or via is left as is and not filled, solder would wick through the vias during the assembly process and starve the pad of a solid, reliable connection. Via in pad is particularly suited for in LED board applications because it provides a highly conductive path for heat dissipation from the heart of the LEDs to cooler regions of the board, like power and ground planes.

When it comes to designing via in pad technology in an LED board, the following steps are important for the PCB designer to follow; via hole size should be small, around 6-8 mils. Vias should be placed on a 25-mil grid and they should be electrically connected to one of the copper planes on the internal layers and preferably on the bottom layer of the board, as well. Fab notes should properly identify the via types that will be filled and plated during manufacturing. Unfortunately, in some cases, naïve, inexperienced PCB designers either fail to realize the importance of via in pad for small, densely populated boards like LED PCBs and don’t use it or they use via in pad incorrectly creating unnecessary issues. Those issues include not using the correct via size; the correct amount being 6 to 8 mil vias. In other instances, the PCB designer designs only a few vias. Here, those very few vias have limited thermal connectivity so they should be used generously. Also, vias are sometimes not connected to large, low resistive copper planes. Lastly, vias can be improperly identified in a fab drawing and can be missed during the filling and plating process. This may result in some or all vias being open, causing soldering issues during assembly such as solder wicking and shorts.

About the Author Zulki Khan is the Founder and President of NexLogic Technologies, Inc., San Jose, CA, an ISO 9001:2008 Certified Company, ISO 13485 certified for medical electronics, and a RoHS compliant EMS provider. Prior to NexLogic, he was General Manager for Imagineering, Inc., Schaumburg, IL. He has also worked on high-speed PCB designs with signal integrity analysis. He holds B.S.E.E from N.E.D University and M.B.A from University of Iowa and is a frequent author of contributed articles to EMS industry publications. ■

Modern Printed Circuits

Weigh Design Ch

Sol

on Microwa Strategies for soldermask at the design stage influence fabrication yield, which ultimately governs PCB cost.

TECH ARTICLE

hoices for

ldermask

ave PCBs BY ATAR MITTAL

DESIGN AND ASSEMBLY DIRECTOR, SIERRA CIRCUITS (www.protoexpress.com)

PTFE-based PCB laminates have long been the materials of choice for rf and microwave circuits because of their low loss tangents in those frequency domains. Though the processes to fabricate boards with PTFE-based laminates differ in several respects from those for conventional FR4 materials, they are generally well-established at manufacturers and well-documented by the material suppliers with few exceptions. One aspect that may be unfamiliar to many PCB designers involves the treatment of copper post-etch and the implications for design to ensure good manufacturing yields.

Modern Printed Circuits

Fig. 1

Soldermask dams surround pads on this microwave board, which was designed using Altium tools.

Whatever laminate is used, PTFE or otherwise, the copper remaining after etch must be cleaned or automated optical inspection to detect trace shorts or opens will be unreliable and soldermask will not stick. The best way to clean the copper is an abrasive scrub. However, all the suppliers of PTFEbased laminates advise that the laminate surface fresh from copper etch is best for adhesion and is compromised by scrubbing. There are alternative cleaning methods, though none are as satisfactory as scrubbing to support AOI of the copper and soldermask adhesion. Consequently, the copper is scrubbed before inspection. A plasma process is used after the scrubbing to reinvigorate the exposed laminate, to return the â&#x20AC;&#x153;toothâ&#x20AC;? to the surface so that soldermask will adhere, if it is an outside layer, or to aid subsequent lamination. However, the plasma oxidizes the copper, so it must be cleaned again if soldermask is to be applied. To avoid compromising the PTFE laminate surface by another scrubbing, a chemical clean for the copper follows in lieu of scrubbing, in preparation for soldermask. The panel must be dried immediately to eliminate moisture that could stain the copper and thereby inhibit soldermask adhesion. The process is a balancing act. Sometimes it does not work and the soldermask has to be stripped, the panel cleaned again and dried, and the soldermask reapplied. Instead of the standard practice of covering a board in soldermask (leaving openings for pads and so forth) rf and microwave designers commonly soldermask only the circuitry (except for the pads,etc) leaving the PTFE laminate surface open. The copper can be scrubbed, AOI can be performed successfully, the soldermask is applied to the copper where it sticks, and there is no need to worry about it on the laminate because it develops off. Another common approach is to restrict the deposit of soldermask to little dams next to pads, which limit solder from traveling down the traces (Figure 1). This approach may be easy to implement for simple circuits, but tedious if thousands of dams are required (Figure 2).

TECH ARTICLE

A Third Design Choice The need for scrubbing or chemical cleaning of the copper can be avoided altogether, and therefore the need to plasma treat the surface of the PTFE dielectric if a lamination will follow, if gold is plated over the copper before etch. The gold does not oxidize, remaining bright after etch, so does not require cleaning to be ready for AOI. Furthermore, a full soldermask with conventional solder openings can adhere to the board. Of course, gold is expensive, but one (or more) cleaning processes and a plasma process are eliminated. There is with gold the issue of copper migration to consider as well. Over time, copper and gold tend to diffuse into each other, the copper brought to the surface oxidizes, and contact resistance increases as a result of the oxidation. Higher temperatures accelerate the process. Nickel ordinarily is used as a barrier layer between copper and gold to prevent diffusion, however nickel cannot be used for rf and microwave circuits. At rf and microwave frequencies, the skin effect predominates in conductors: Most of the current flows in the outside of traces. Nickel is a lossy metal compared to copper especially at high frequencies, and the skin effect would tend to concentrate much of the current through the nickel near the trace surface. Copper diffusion into gold really is not a problem, unless the fabricated boards are kept in inventory a long time before assembly. Once components are soldered to their goldplated contacts, there is no worry about contact deterioration. Regarding the cost of gold, the plating amounts to a few microns thick. If thereâ&#x20AC;&#x2122;s a plane on one side of the board, that would involve slightly more expense (more gold) than a signal layer, of course. Yet, there are fewer process steps with full-body plated gold. The copper is simply plated and then etched, with the gold as an etch resist, leaving the final metal surface finish. Yield ultimately governs the cost of fabrication.

Fig. 2

Modern Printed Circuits

Constra

COVER INTERVIEW

aint-Driven

Design Hemant Shah Director of Product Management for Allegro PCB Products at Cadence

The Allegro PCB Designer from Cadence is a design environment that takes complex designs from concept to production. The ease of use of this system allows engineers increase their productivity by reducing the amount of design iterations. With Allegro, designers can cost-effectively match the technological needs of both small and large companies. We spoke with Hemant Shah, the Director of Product Management for Allegro PCB Designer, about the benefits of using a constraint-driven design program, some of the unique features of the system, and how it adapts to the ever changing needs of the industry.

Modern Printed Circuits

“ One of the reasons why Allegro is the best tool on the market is because we are very customer driven and we listen to what the customer needs are.” Can you explain constraint driven design and why is it the leading product for high-speed design?

Fundamentally, the idea is that you want to capture the design intent. Traditionally, people used to just send netlists from schematic capture tools to the layout tools and the layout tool would take that netlist and do the layout. As designs started to have high-speed signals on them, the design intent was more than just connectivity; it is connectivity plus the constraints similar to what you mentioned, how long a trace can be for it to function correctly. There are many additional constraints that need to be put into the design by a design engineer for the layout designer to do the job right, the first time.

What would happen if you didn’t have a Constraint driven design system that checked all of those constraints as you layout the board, you would find the problems in the lab in the prototype and would have a physical prototype iteration, which is very expensive both time wise and dollars wise. What the Constraint driven design flow does is not only allow you to capture the constraints, but guides your design throughout the implementation process to ensure you are adhering to those constraints. The number of constraints that we handle has grown steadily based on the customer feedback driven primarily by advanced interfaces (like DDRx etc) and our adherence to that and guidance based on the implementation has also grown.

The whole notion behind constraint-driven design is to have the complete design intent embedded in the design so that it is transferred from design engineer to layout engineer, but more importantly, layout the design according to the constraints. As I am laying out these printed circuit boards, I am guided by the system to say whether my design is adhering to the constraints or not. Traditionally, what used to happen is that people would do layout then do analysis, and then resolve problems that are detected through analysis – which results in layout-analysis-layout kind of iterations. What the constraint driven design process does is eliminate these iterations.

One of the reasons why Allegro is the best tool on the market is because we are very customer driven and we listen to what the customer needs are. For example, we start working of DDR4 with the semiconductor accompanies before the DDR4 goes out to the market and the system companies start to use it. This is one of the strengths that Cadence has; because our customers also include the semiconductor companies, that creates these constraints when they come out with new devices, so we embed those into our tools and allow the system designers to create designs that will meet constraints with the first prototype.

COVER INTERVIEW Are there any other exciting features that have been ncluded in the tool in the last few years? There are a few of them I would like to talk about. Initially, what we came up with is a way to give feedback to the PCB designers as they were routing a trace for example. Imagine a simple case of where you would look at the max length—you would say this particular trace should not be longer than so many mils. We provided heads up display on the screen to give the user feedback, so as the PCB designer is routing a trace they would be able to see if they are meeting the constraint or not. As more constraints came in, we started to give them two or three rows of heads up display; one would be the relative delay compared to your critical signal. For example, in the DDR interface you would have clock and strobe and you might want to match your signals to the clock or the strobe and so on. We started to provide the feedback through the heads up display. As the number of constraints grew as these interfaces became more complex—DDR2 was very complex, DDR3 simplified a few things and DDR4 further simplified things— but advanced interfaces are adding a lot of constraints for the user to follow. What we came out with recently was a way to provide even more feedback to the user through what we call Timing Vision. In Timing Vision what we do is color code signals on the

canvas itself. Instead of looking at constraints in a constraint manager and going back and forth between the canvas and the constraint manager, we color code the signals on the canvas to show the current status. For example, you would route a DDR2 or DDR3 interface from pin to pin, and each of the byte lanes would have some signals that would meet constraints and some that do not. Colorcoding allows getting the feedback from the system to the designer on what timing issues need to be addressed. Timing Vision is much more than a color coding system, because underneath we have is an intelligent system that looks at all the constraints and it provides not only color coding information, but also gives you feedback on what you should do with some of the signals – elongate some and shorten others to meet timing constraints.

Could you elaborate more on Timing Vision’s features? In addition to Timing Vision, we have come up with a couple of additional tools that we call auto-interactive tools. All previous PCB design tools have had interactive capabilities and the EDA industry has always had some form of automatic routing capability. But as the constraints increase in complexity, the routers tend to have limited success. If you apply the automatic tools in an intelligent manner in subsets, they tend to be successful.

Timing Vision Software

Modern Printed Circuits

“ Recently, a customer came forward and said that they were able to slash 67% of their time off when they tuned with the Auto-interactive Delay Tuning capability.” What we found is, as the complexity increases, the designer is really the one that has the experience and intuition to apply the tools in a specific manner to be more successful more efficient and get the designs out faster. What we have done over the past few years is to introduce new technology that combines the intuition of the PCB designer with the automation for routing, tuning. This kind of technology is called Auto Interactive Technology. Using my previous example with the byte lanes, if you look at the byte lanes and you say ‘I have some high-speed signals routed pointto-point and now I want to tune them to meet the timing constraints.’ We have a utility called Auto Interactive Delay Tuning. It allows the user to pick a subset of the interface to tune. It allows the PCB Designer to tune Signals or byte lanes in a particular order that the designer thinks makes sense. The designer knows how

to utilize the PCB design space better and they want to tune or route signals in a particular order. This gives the control to the PCB designer and then when he selects the byte lane the Auto-interative Delay Tuning technology automatically tunes the signals within that byte lane. The other utility that gets used before the Auto Interactive Delay Tune is Phase Tuning. All of these DDR interfaces have differential pairs that need to be phase tuned—static and dynamic phase have to be met. Unless you meet those phase requirements, it doesn’t matter how you meet timing on the rest of the byte lane. PCB designers use the Auto-interactive Phase Tuning to meet the static and dynamic phase requirements first then you use the Auto Interactive Delay Tuning on the byte lanes or the complete interface as a whole. Recently, a customer came forward and said that they were able to slash 67% of their time off when they tuned with the Auto-interactive Delay Tuning (AiDT) capability. It’s a huge success that we have had with AiDT.

I imagine that part of the challenge and the value in what you have developed here is just making it a good interface that an engineer can interact with the Auto Router and these constraints. Absolutely right. I just wanted to add that the auto part is hidden, user selects the signals (s)he wants to tune, and everything else is done under the hood. In other words, there is no set up there is no running another utility, another tool. This is why we think with the Auto Interactive technology we have is unique. It doesn’t make the user feel like they are running an automated tool in fact it feels like they are running interactively and the power of the automation is at their fingertips.

Are there any other features or technology in Allegro that you would like to touch on? There are two more that I would like to talk about; one is ECAD-MCAD Co-Design. This is an area we keep innovating and keep improving. A few years ago, a new standard emerged called EDMD Schema. EDMD stands for Electronic Design Mechanical

COVER INTERVIEW Design, and it’s the new standard and the next generation of IDF. IDF used to be used as a file format to exchange data between PCB design and mechanical design. New Schema came up and it was more than a Schema in that the notion was to do collaborative and co-design. PCB designers want to be able to send just that incremental change back to the mechanical designer. IDF did not have this capability. This new standard EDMD Schema is most commonly referred to as the IDX format. IDX gives the PCB Designer and Mechanical Designer a way to exchange incremental data. For example, if a mechanical designer moves the mounting hole because he needs to make a change in the housing, if that mounting hole happens to be in the middle of a component that cannot be moved, for electrical reasons the PCB Designer has a way to reject it and put a comment there ‘If I move the component, the design will not function etc,’ or vice versa. If a PCB designer puts a tall component in a region that doesn’t really fit in the enclosure, the mechanical designer can tell the PCB designer to fix it. You can do that kind of collaboration going back and forth. The other one is in the are of passign Design Data to Manufacturing. ECAD-MCAD CoDesign and what I am about to talk about is available in the OrCAD PCB Deisgner as well because we think this is also something each PCB Designer needs to have. These are areas that we innovated on both of those areas. This particular one is a standard that has been out there for a while called IPC2581.

Why don’t you explain what IPC2581 is? 2581 is a standard that was designed to improve the way design data is transferred from design house to manufacturing house. traditionally designers use Gerber files, Drill Files then you have to have a Test File then a Read Me File. In one of the things we found was that no one was using it, so we created a consortium called the IPC2581 consortium. You can actually go to the website and look it up at IPC2581.com. It is a consortium that was initiated by Cadence and then we had 12 founding members that, that actually created the consortium. The IPC2581 consortium has been very active since May of 2011. One

example of what we are innovating on is the ability for a PCB designer to exchange stack-up data with the fabricators before the PCB layout begins. This is very important if you are dealing with any kind of controlled impedances on your board or any kind of board with high-speed signals.. This kind of interaction happens between the design house and their fabricator on what materials to use, what the stack up is going to look like, and the thickness of the layers etc. Today, this exchange happens through e-mails, Excel spreadsheets, Powerpoints, and combination of those things. With this 2581 standard, you will be able to go from design house to the fabricator or vice versa electronically so you don’t have to have a bunch of files describing what the stack up should look like and the users don’t have to manually enter it (into the CAD tools). This is one of the innovations the consortium made in the 2581 format and the improvement to the format was made within 1 year. The updated spec was released in early October this year. What it does is take the manual effort out of the picture, when you are specifying the stack up into a PCB layout. This capability will be released in Allegro in January.

Where do you see Allegro heading over the next few years in terms of the market and user feedback? I think there are two areas that we see changes in. One is what we call miniaturization trend; all of us are familiar with smart phones and tablets. It is the miniaturization trend that is happening in multiple ways in different industries. Now what does that mean? It means you are putting more functionality in smaller devices and making them smarter. Wider adoption of that technology trend is going to happen in the next few years. This means that if you’re high-end consumer electronics maker are you going to start to embed components in inner layers of PCBs. If you are in the higher consumer electronics space, are you going to deal with the ridgidflex. Allegro has been handling ridgid-flex quite some time now and we will continue to enhance that capability. ●

Modern Printed Circuits

Full PCB Design

Ecosyst

Josh Moore Director of Product Marketing for OrCAD Solutions at Cadence

Cadence also offers a powerful, intuitive, and integrated OrCAD solution that helps designers successfully meet project goals. The Cadence OrCAD PCB Designer is production proven, scalable, and robust with broad ecosystem support. The OrCAD solution offers combined capabilities from an extensive list of worldwide network and channel partners to achieve superior customer support. We spoke with Josh Moore, Director of Product Marketing for Cadence's OrCAD solutions, about their differentiated PCB design solutions, some of the new features added to the ecosystem, and what the future has in store for Cadence's OrCAD ecosystem.

COVER INTERVIEW

tem

Modern Printed Circuits

How does OrCAD fit in with Cadence’s product line and what is the difference between an enterprise product and what OrCAD might be for different types of audiences? OrCAD was acquired back in 1999 by Cadence, just a little before my joining Cadence. At the time they purchased OrCAD, the OrCAD technologies, what we call the traditional OrCAD technology, comprised of OrCAD capture, for schematic entry, PSpice for analog and circuit simulation, and a product for PCB layout called OrCAD Layout. After the acquisition, there were several years of integrating the technologies between the Allegro products and the OrCAD products to share the technologies across the different product lines. Traditionally, OrCAD has always been aimed at what we call the mainstream market, which is a general type of user, more so than what Hemant’s audience is, which is what we call the enterprise user. Think of the mainstream users as everyday users; they may be a one-man-band doing a little bit of everything, they may be a consultant, maybe a smaller company with just a few employees or even a medium sized company, but not the scale of the enterprise companies that may have hundereds of designers and engineers and specialists and all kinds of stuff geared towards the higher end of the market. These are the kinds of companies that develop everyday consumer appliances, industrial equipment, power supplies, and those kinds of things. We see the market as highly segmented across those two audiences and tailor the products accordingly. The OrCAD branded products are aimed at those customers that tend to be more price-sensitive and productivity oriented. It’s your average productivity automation kind of technology that their looking to get their job done that they do day-in and dayout. Because they’re going to spend all day

routing a board or draw a schematic and turn around the next day and do some kind of simulation—it’s a little bit of everything. Within Cadence what we’ve done as far as the integration, is utilize the technology across both of those product lines and brands. For example, we’ve talked a little bit about how the PCB environment across Allegro and OrCAD is the same technology. What we call PCB Editor, which is the place and route canvas for the PCB tool, is the same PCB canvas both in the OrCAD product line and in the Allegro product line. The difference is the features, whether they are a set of features aimed at the mainstream user or a set of features and capabilities aimed at the enterprise user. The use model is the same, the canvas is the same, the libraries are the same; literally everything is the same. The only thing that changes is the license file. When a user needs more capability within the OrCAD space or if they want to move up to the Allegro space as their products evolve or as their business evolves, they can just simply change license files and have new menus appear, new functions appear—but everything is the same. We do something similar with the signal integrity products and with the front-end products; we share technology across the OrCAD and Allegro product lines. In the OrCAD space, schematic capture called OrCAD Capture; In the Allegro space schematic capture is called Allegro Design Entry CIS. Same Capture based technology, just branded and marketed differently to a different set of users.

Are there any features that have been included in OrCAD recently? Yes. I will touch on a couple of things from our last release that are kind of the big nuggets for our mainstream customers. The first was around the PSpice product for analog and

COVER INTERVIEW circuit simulation. One of the things that we have been focusing on for the last couple of years is a serious step up in evolution in terms of speed, performance, and convergence. One of the things we focused on to improve the overall speed was to introduce a multicore solution for PSpice in the last release. This had the obvious advantage you would think of in terms of having more processing power that users could bring to bear against the circuit being to simulated. Across the board, it was generally a 20% improvement that we saw from the multi-core capabilities. But in terms of processing power coming to bear against larger designs and designs with more complex models like MOSFETs and BJTs, the improvements were markedly more than that simple 20%. We saw increases of about 60-70% for those kinds of complex designs. This is simply because there is more going on with those larger designs, and more complex models, and having more processing capability really sped that up. Since you can’t really buy a modern computer these days that doesn’t have more than one core, it was a performance improvement that everybody saw right away—they didn’t have to go out and buy new hardware, or upgrade anything to take advantage of that.

of a topology file that can be imported into the OrCAD PCB SI tool for further signal integrity analysis. They could draw the circuit, extract it, bring it into the signal integrity tool and then start doing exploration at the design stage to figure out if they have the right values for terminators, or have the right termination strategy. They can also see if they need to define the PCB layout rules and constraints relative to the length that a particular signal has to be, and what layer it has to go on. They can drive all that from the front end and make the whole process a little easier with this automated flow between the schematic action tool and the signal integrity tool.

Can you just elaborate a little bit on OrCAD PCB SI tool and its capabilities? Josh: The tool is amply named OrCAD PCB SI. In the OrCAD space, for the mainstream customer, it’s geared towards doing basic to moderately complex signal integrity analysis. It’s mainly for single signals or even small amounts of coupled signals, differential pairs, one or two aggressor and victim crosstalk kinds of evaluation. The capabilities are basic signal integrity, for termination, for signal quality, reflection, that kind of stuff. There’s also crosstalk capability, differential pair analysis.

The second major improvement since we had introduced signal integrity into the OrCAD space, several years ago now, we wanted to build integration between the OrCAD Capture tool and the OrCAD PCB SI tool. This enabled the engineers who were drawing the schematic and wanting to do circuit analysis for signal integrity to not have to manage those two environments independently and manually. In the last release we built a flow between the OrCAD Capture tool and the OrCAD PCB SI tool such that as a the engineer is drawing a circuit he can simply select that circuit, and define the models that identify the drivers or the discretes or the receivers, and then have the system automatically extract that information in the form

PSpice Screenshot

Modern Printed Circuits

STEP Capability

Does OrCAD offer scripting integration for PSpice? Yes. Back several releases ag, we introduced a TCL scripting capability into the OrCAD Capture product that allowed customers unprecedented access to the database, the architecture, the command infrastructure, and the GUI associated with the Capture product. Short of giving everybody the source code to Capture, through this TCL integration, customers have access to literally the nuts and bolts of Capture to customize it, to their hearts content. They can change the GUI in the commands, invent their own commands, import, export and manipulate data, and create custom flows. It’s really been a game changer for us in terms of what customers can do to make their Capture environment their own. It’s very analogous to the kind of platform messaging you hear with your favorite mobile device. Your favorite table or smart phone depending on the operating system is really a platform for whatever you want to make it. Sure it surfs the web and makes phone calls, but the apps that you can load up and the customization capabilities make it a lot more than just a phone or a tablet and is really kind of what distinguishes those modern technologies from what we had just a few years ago where it was just a phone.

In the last release, we extended that TCL integration to PSpice. Now customers have acess to the PSpice GUI, the simulation data, and the algorithms themselves. They can actually manipulate the way the algorithms behave and what they do during simulation. You can even introduce your own algorithms and your own data into your simulation. For example, you could do something like a simulation of particular power supply circuit that’s going into a satellite. But, I need to account for the temperature swings that happen as it’s rotating around the earth and I want to find a way I want to figure out what the radiation effects are five years from now. I’ve done an external calculation that figures out radiation effects on component values or voltages or battery life, and I can feed that into the simulation at any time I want. It gives customers an unprecedented level of interaction and customization to the PSpice product that they’ve never had before. That’s why it’s been such a game changer for us. When I get into conversations with customers, you always get into the “I really would like the tool to do this,” or, “here’s my wish list or need this added to the roadmap,” or whatever happens to be, and the conversation was always basically the same.

COVER INTERVIEW Now the conversation is, “Thanks for the input. We might be able to do that for you tomorrow or one of our vendors or partners might be able to do that. Or if you have somebody that knows programming – the TCL programming language isn’t that much different than a couple of other programming languages like Python. If you know programming the answer is now “yes” instead of the “no, maybe late.” Between our channel partners that service the OrCAD product or a CAD support person within a company itself, we can generate new capabilities literally the next day, and in some cases we have. It really just changes that entire conversation with the customer who wants something that might be benefit to everybody or wants something that’s specific to the way they do things.

What is the STEP Capability with OrCAD? Earlier this year, we introduced a STEP capability for 3D model support and viewing capability within the PCB products. As customers have gotten more and more into the co-design between the mechanical world and the electrical world, there wasn’t a lot of interaction between those two worlds until capabilities like IDX came along or before that it was IDF. Now with STEP, you’ve got 3D models and model accurate representations of the components that are on the PCB itself. That can be shared with both the guy who’s doing the PCB layout in the electrical world and also his mechanical counterpart in the mechanical world to collaborate on things like component placement, enclosures, collisions and other obstacles that may interfere between the electrical and the mechanical world. This has been a fairly recent release for us, but it has been, especially in the OrCAD space, one of the more well-received updates that we’ve done in the PCB space. Models are readily available for a user to map their PCB components with model accurate 3D representations. And they gets to see a little bit about board in terms of what the mechanical guy sees and they can import enclosures from the mechanical world to see how it’s all going to fit together and they can immediately see if they’ve got a component sticking up through the enclosure that’s not where it’s supposed to be.

What type of changes or direction do you see the OrCAD product line changing over the next few years? Mainstream is where high-end technology eventually winds up. The changes that we see are very similar to the kinds of changes that we’ve always seen where technology that used to be very bleeding edge, used by just a few people, a few types of companies, becomes more the norm for anybody and everybody doing whatever types of designs their doing. I always use the example of the classic wall thermostat. When I was growing up it was 100% mechanical. It had nuts and bolts inside of it, you twisted the dial and you got heat or cold. Now, that same wall thermostat has an LCD panel, it’s Internet connected, it’s wireless, it might even be Bluetooth, it’s smart, it thinks, it’s got a microprocessor or microcontroller inside of it—it’s very cool but not built with leading edge technologies. A lot of that technology a few years ago was indeed bleeding edge. A microcontroller wouldn’t have fit inside of something quite that small and quite that cheap, so the technology for us really migrates its way down in the mainstream space somewhat rapidly these days and more so than in days past, such that what is bleeding edge now becomes main stream within a short amount of time. That’s something that we keep our eye on. The kinds of places that we see that happening are in terms of Internet connected and wireless devices that have become far more simple and cheaper than they ever used to be. I’ll give you a good example of one that I heard from a company in India; they got into a business of an Internet of Things device, which turned out to be a refrigerator magnet. You could program this refrigerator magnet with your pizza order. When you walked up to the refrigerator and activated this refrigerator magnet it would connect itself to the Internet and place your pizza order, and sooner or later pizza showed up. But the electronics in this thing probably cost very little to make—they were not terribly complex or complicated. There’s a small radio RF inside of it, very mainstream by today’s standards. But those kinds of things three, four, five, ten years ago were certainly bleeding edge. Those are the kinds of changes that we see and the speed at which those changes occur in today’s market. ●

Modern Printed Circuits

Model

PCB Potentia Usi By David Cuthbert

EEWeb Contributing Author

In this article you Gradients and yo You can then des

PCB traces and resulting in pote are especially im Digital converter a potential gradie

TECH ARTICLE

al Gradients ing SPICE

u’ll learn several techniques to control PCB Plane Potential ou’ll learn how to simulate these techniques with SPICE. sign successful low-level signal layouts on the first try.

planes offer electrical resistance to electrical current ential gradients and signal corruption. Voltage gradients mportant in low level analog circuitry—such as Analog to rs—where measurement accuracy can be compromised by ent of just a few microvolts.

Modern Printed Circuits

The Concept of Squares Let’s begin with the concept of squares. The electrical resistance from one edge to the opposite edge of a square of PCB copper is called resistance per square. Fig. 1 shows a PCB trace composed of six squares. The resistance from the left-most edge of square 1 to the right-most edge of square 6 is six times the resistance per square.

Resistance per Square and Temperature Like all metals the resistance of copper changes with temperature. This is called the temperature coefficient of electrical resistance and for copper it is 3900 ppm/ deg. C. The resistance at temperature T is:

R = R20 + R20 (T − 20)(0.0039)) Where R20 is the resistance at 20 deg C and T is the temperature. For example, the resistance per square of 1 oz. copper at 100 deg C is:

R = 500µ + 500µ(100 − 20)(0.0039) = 656µΩ

Calculating PCB Plane Resistance Fig. 1

Copper Weight and Resistance per Square A handy number to remember is the electrical resistance of 1 oz. copper at 20 degrees Celsius: 500µΩ/square. For other copper weights the resistance per square is inversely proportional to the weight. For example, ½ oz. copper is 1000µΩ/square while 2 oz. copper is 250µΩ/ square. It’s interesting to note that resistance per square is independent of the size of the square and a 100 mil square has the same resistance per square as a 10 mil square. Also remember that 1 oz. copper is 1.4 mils thick. We’ll use this later when calculating Bus Bar resistance.

PCB Plane resistance is not as easy to calculate because it’s not the edge-to-edge resistance that we need to know but the resistance form one point to another. And Spreading Resistance─the resistance due to current spreading out from a small point─complicates the calculation. Additionally, irregular plane shapes such as Fig. 2 add yet another complication to the calculation. While PCB layout tools are available to calculate plane resistance, not all tools do. Fortunately, for those of you who don’t have access to these tools any SPICE simulator can be used.

Calculating PCB Trace Resistance To calculate the resistance of a PCB trace, divide trace length by trace width to obtain the number of squares then multiply this result by the resistance per square. For example, the resistance of a 1oz. trace, 1000 mils in length and having a width of 10 mils is: R=(

Length 1000 (Resistance per Square) = ( )(500µΩ)) = 50mΩ W idth 10

Fig. 2

TECH ARTICLE

Find PCB Plane Resistance Using SPICE To calculate PCB resistance using SPICE a matrix of resistive squares is built. Each square is composed of four resistors each having a value equal to twice the resistance per square.

As illustrated in Fig. 5, to find the resistance 1 amp is driven between points A and B, yielding a potential difference of 390 µV and a resistance of 390 µΩ.

Fig. 3 shows four unconnected 500µΩ squares. When the four squares are connected together, as shown in Fig. 4, resistors that touch are connected in parallel and the resistance is halved.

Fig. 5

Potential Gradients

Fig. 3

While the resistance between widely separated points is useful to know, it is the potential difference between close points - caused by current driven between other points – that can drive a PCB layout. To determine the potential gradient in V/inch, measure the potential difference between the two points of interest and divide by the distance between the two points. In low level analog instrumentation, current passing through sensitive areas produces a voltage gradient that can corrupt measurements. For example, a 16-bit ADC having a full scale voltage of 1.25 volts experiences a 1-LSB error for a PCB gradient of only 19 µV. Exploring plane potential gradients in SPICE can help quantify the steps that can be taken to minimize these gradients. Some of the steps to reduce potential gradients are:

Fig. 4 Now that we know how to construct a PCB plane model in SPICE it’s time to find the resistance between two points.

• Increase copper weight • Add plane layers • Add a bus bar to bypass current around sensitive nodes • Move power connectors • Move high current loads • Arrange sensitive nodes along an equipotential line • Add a slot • Add a moat

Modern Printed Circuits

While many PCB designers know about these methods, and can arrange circuits accordingly, they don’t have a tool to quantify a particular layout. The result of working without a tool can be: moving nodes farther than needed, unnecessarily increasing copper weight, adding unneeded bus bars, adding unnecessary slots and motes, and other circuit changes that increase cost.

of a 10 mil thick bus bar is 70µΩ/square. To build a model of Fig. 7 in SPICE the plane is built up with a resistor matrix and the resistors along the bus bar path are changed to 70µΩ.

Referring to Fig. 6, to determine the potential difference between 1 and 2, drive the appropriate current between A and B and measure the potential difference between 1 and 2. In this example the potential between points 1 and 2 is 55uV and the distance between them is 0.5 inches, giving a potential gradient of 110uV/inch. P otentialDif f erence 55µV P otentialGradient = = = 110µV /Inch Distance 0.5”

Copper Weight and Additional Plane Layers Using heavier copper or adding plane layers is a common but expensive and brute-force way to reduce Potential Gradients. We’ll learn several techniques that don’t add cost but can still reduce Potential Gradients.

Fig. 7

Move Connectors and Loads An example of moving the power connector or the high current load is shown in Fig. 8. Moving power connector A reduces the potential gradient between points 1 and 2 to just 1uV/inch.

Fig. 8

Arrange Sensitive Nodes Fig. 6

Bus Bars Fig. 7 illustrates a Bus Bar (the grey line) used to conduct high current between two points. Bus bars are useful when increasing copper weight and/or adding layers is too expensive or impractical. Bus bars are modeled in SPICE by setting the resistors under the bus bar to the appropriate values. Bus Bar resistance is not always specified and so you’ll have to calculate it. Bus bar length and width is known and the number of squares can be calculated but Bus Bars are specified by thickness and not by copper weight. Remembering that the resistance of 1 oz. copper is 500µΩ/square and that it’s 1.4 mils thick, we can calculate the resistance per square of a copper bus by dividing 1.4 mils by the bus bar thickness. For example, the resistance

Another way to reduce the potential gradient is to arrange the sensitive nodes along an equipotential line. Moving the sensitive nodes from the configuration of Fig. 6 to the configuration of Fig. 9 reduces the Potential gradient from 55µV/inch to zero.

Fig. 9

TECH ARTICLE

Fig. 11

Plane Slots A Plane Slot is shown in Fig. 10 with the high current path endpoints represented by A and B. The two sensitive nodes are 1 and 2. The Plane Slot reduces the potential gradient adjacent to the slot from 110 to 40uV/inch. The potential gradient per inch, adjacent to the slot, is graphed in Fig. 11.

Moats with Draw Bridges A Moat and Draw Bridge as shown in Fig. 12 is a powerful tool for taming potential gradients. Inside the moated area the potential gradient is nearly zero whereas it was 120µV/inch without the moat.

Fig. 10

Summary We’ve learned how to model PCB Plane Potential Gradients using SPICE and we’ve learned several techniques to minimize them. This should help you to design good boards the first time saving the time and money spent on troubleshooting and board spins. ■ Fig. 12

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