Modern Printed Circuits: October 2015 by EEWeb Magazines

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Modern Printed Circuits

EDITORIAL STAFF Content Editor Alex Maddalena amaddalena@aspencore.com Digital Content Manager Heather Hamilton hhamilton@aspencore.com Tel | 208-639-6485 Global Creative Director Nicolas Perner nperner@aspencore.com Graphic Designer Carol Smiley csmiley@aspencore.com Audience Development Claire Hellar chellar@aspencore.com Register at EEWeb http://www.eeweb.com/register/

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TECH REPORT Building Differentiated Products Through Shorter, More Predictable Design Cycles EEWEB FEATURES Circuit Protection Components from Littelfuse Meet Stringent Safety Standards Breaking Out the BGAs Overview of Stencil Design New Ultra-flat GDT Technology INDUSTRY INTERVIEW

PCB Prototyping Made Easy Interview with Stephen Garcia— Building Products Through Shorter, More Predictable Design Cycle President of BayDifferentiated Area Circuits

Published by AspenCore 950 West Bannock Suite 450 Boise, Idaho 83702 Tel | 208-639-6464 Victor Alejandro Gao General Manager Executive Publisher Cody Miller Global Media Director Group Publisher

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Figure 6: Reduce layer counts and shorten design cycle through design planning

Accelerated timing closure

Application Note:

42 Enhancing Workplace Safety in Hazardous 26 L

As the data rates increase and supply voltages decrease in today’s advanced interfaces, PCB designers spend more time to ensure signals in an interface meet timing With increasing density PCBs, the effort to get withrequirements. PICO® 259-UL913 and 305onSeries Intrinsic Safety to timing closure—ensuring all signals meet timing requirements—can increase significantly. To meet this increasingly complex challenge, you need an environment that allows you to graphically see real-time delay and phase information directly on the routing canvas – timing vision. Traditionally, evaluating current status of timing/length of a routed interface requires numerous trips to the constraint manager and as well as reviews of other current properties. What would be helpful here is a system to evaluate complex timing constraints and interdependencies amongst signals that show the current status of a set of routed signals—a DDRx byte lane or a complete DDRx interface. Ideally, you’d have information that defines the delay problem in the simplest terms possible.

Additionally, you need a way to leverage the feedback from the system to tune differential pairs and meet timing constraints on byte lanes as well as control and address bits, preferably in a way that reduces the manual one through tuning and adjusting. Ideally, you’d drive the strategy and execution, but have the computer do the bulk of the work to meet complex timing constraints. Such an auto-interactive strategy can allow you to tune advanced interfaces like DDRx in significantly less time compared to using traditional, more manual methods.

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Building

DIFFERENTIATED PRODUCTS Through Shorter, More Predictable DESIGN CYCLES By

TECH REPORT

To position themselves for growth in todayâ&#x20AC;&#x2122;s market, systems companies need to build highly differentiated products; reduce time to market; and focus on compliant, environmentally aware designs. This article addresses the first two challengesâ&#x20AC;&#x201D;the needs to build differentiated products and reduce time to market. It also discusses new design techniques, processes, and methodologies that can reduce design cycles by as much as 40-percent.

Modern Printed Circuits

INTRODUCTION rentiated Products Through With the recent global economic Predictable Design Cycles slowdown, system companies are facing

shrinking markets and prospects with less available budget for purchasing new or the latest electronic products. Given the recent owth in today’s market, systems companies need topre-downturn build highly health of the global electronic systems ce time to market; and focus on compliant, environmentally aware market, many healthy high-growth the first two challenges—the needs topreviously build differentiated products and solvent and companies are facing discusses new design techniques, processes, methodologies thatrapidly declining sales and associated revenues, s much as 40%. deeper discounting, smaller order sizes, longer sales cycles, and increased (even hostile) competition. Many companies are making expense reductions, cancelling new or advanced projects, and reducing Introduction overhead through workforce downsizing. With the recent global economic slowdown, system companies are facing All of these measures are, offorcourse, shrinking markets and prospects with less available budget purchasing .. 1 new or the latest electronic products. Given the recent pre-downturn necessary in order for a business to health of the global electronic systems market, many previously healthy high-growth maintain its viability. However, these .. 2 and solvent companies are facing rapidly declining sales and associated alone will not drive in bottomrevenues, deeper discounting, smaller order sizes,growth longer sales cycles, and line revenue orcompanies market share. Instead, increased (even hostile) competition. Many are making expense .. 2 reductions, cancelling new system or advanced projects, and reducing overhead through companies are increasingly workforce downsizing. All of these measures are, of course, necessary in order 10 focusing on addressing a number of for a business to maintain its viability. However, these alone will not drive growth business challenges that, if managed in bottom-line revenue or market share. Instead, system companies are increassuccessfully, can help them survive. At ingly focusing on addressing a number of business challenges that, if managed successfully, can help them a macro themost three common most common a survive. macro At level, thelevel three challenges are shown in Figure 1 below: challenges are shown in Figure 1 below:

Building differentiated products

Getting products to market

Environmentally aware

Figure 1. Macro-level business drivers. Figure 1 Macro-level business drivers

This article will focus on the first two challenges: building differentiated products, which can enable systems companies to quickly penetrate a market, take a leadership position, and effectively counter or displace any competition; and building them faster. Clear differentiation also allows a superior value proposition, which will enable a stronger position on pricing with less need to succumb to eroding ASPs. Differentiation can involve many factors, but this paper will focus on those related to the technology impact /usage that directly enables the design of products with shorter, more predictable design cycles compared to the competition.

NEEDS EVOLVE WITH NEW DEVICES AND ARCHITECTURES Ever since design automation tools were invented, the EDA mantra has been shorter design-cycles. First, EDA tools were compared to an Etch A Sketch, and then they were compared to themselves—previous generation tools and methodologies. So, should every release of the software just be compared to its previous version? The answer, obviously, is no. The most important comparison of a particular release of EDA vendor’s software is to compare it to the user’s / company’s design needs—i.e., How well does the new release of the PCB or IC packaging software address the design challenges the end users have? A company’s design needs evolve as the products and services a company offers evolve. Every company wants to differentiate its offerings from its

TECH REPORT competitors, and get its products to market faster, cheaper, and with more functionality. Systems companies are also impacted by new ICs and design methodologies offered by the semiconductor industry. A good example is the introduction of serial links—such as PCI Express®, Serial ATA—which change the architecture of signals on PCBs from parallel interfaces to serial interfaces. Another good example is the increasing capabilities and capacities of FPGAs, which shorten the design cycle time for system designers but add additional design challenges (pin assignment time, and increased number of iterations between PCB layout designer and FPGA designer). Pressures to reduce development costs while shortening design cycles have been forcing many companies to use low-cost geographies to do PCB designs. Semiconductor companies often introduce new devices, interfaces, and architectures that are intended to help their systems company customers in shortening the design cycle or offering improved performance. Since their ROI lies in developing solutions that apply to the majority (not just the early few), EDA vendors and their tools tend to lag adoption of such new interfaces and architectures. When such changes are driven by standards, EDA companies can be sure that changes they make to support new interfaces—such as DDR3, DDR4, PCI Express Gen3, USB 3.1 etc.—will be applicable to a broader customer base.

When there is a need that is not supported by EDA vendors, many companies customize and/or extend EDA vendors’ tools to address their immediate needs while they wait for their EDA vendors to catch up and fill the gap. In such cases, end users need a system that is easily extensible and an EDA vendor that supports end users’ abilities to extend and customize the tool capabilities quickly and reliably. Sharing your long-term design challenges roadmap (not your end product roadmap) makes your vendor a partner, and often allows appropriate roadmap alignment to address your needs sooner, rather than later. You should have an ongoing communication with your partner/ vendor on what and how future releases being developed helps you to get what you need to shorten your design cycle.

WAYS TO ACHIEVE SHORTER, MORE PREDICTABLE DESIGN CYCLES How do PCB and IC packaging customers shorten their design cycles? There are several ways companies achieve shorter, more predictable design cycles. Although approaches vary depending on the size of the company, the market segment that the company belongs to, and its competitive position within that market segment, here are some common themes:

Every company wants to differentiate its offerings from its competitors, and get its products to market faster, cheaper, and with more functionality.

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Eliminate Unnecessary Design and Physical Prototype Iterations Deploy a Constraint-driven Design Flow

Develop constraints through simulation to enable a constraint-driven design flow. This involves using solution space exploration to ensure development of optimal constraints for your design— these constraints, in turn, ensure that your product performs at its peak in various operating conditions. This upfront investment helps avoid iterations at the tail end of the design cycle, which could make it harder to predict when the design will be completed.

Design Cycle Time

All EDA systems provide a way for incorporating traditional design manufacturing rules. Over the years, such systems have evolved to provide real-time feedback on such traditional rule adherence as the design is created and manipulated. This is the baseline. With the introduction of new devices and architectures, new design rules have to be followed. For example, using The cost of not developing such a differential pairs provides some electrical Building Differentiated Productscan Through Shorter, More Predictable constraint-driven design flow either advantages; they also introduce additional lead to several physical prototype the rules for all such signals on your board is important. Similarly, as the manufacturing process for your desi rules for physical implementation of such evolves, you need a system that can combine such new rules for in boththe manufacturing iterations with debugging lab and electrical domains guide the design as it is being developed. Having an iteration at the tail end of the design cycle—either for lack signals. Rules required to route serial electrical rulesor, adherence or for lack of manufacturing finding rule adherence—makes the design cycle long and, wo worse, customers problems unpredictable. links such as PCI Express Gen2 versus with your design. cost ofdesign physical Develop constraints through simulation to enableThe a constraint-driven flow. This involves using solution sp exploration to ensure development of optimal constraints for your design—these constraints, in turn, ensure th rules required for parallel interfaces such prototype iterations varies among your product performs at its peak in various operating conditions. This upfront investment helps avoid iteration the design cycle, which could make it harder to predict when the design will be completed. as DDR3 and DDR4 are very different. the tail end of customers in different geographies; The cost of not developing such a constraint-driven design flow can either lead to several physical prototype ite Often a system these days includes both tions with debugging lab or, customers problems with your design. The cost of physical timein the lost inworse, doing anfinding iteration ranges iterations varies among customers in different geographies; time lost in doing an iteration ranges fro serial and parallel interfaces. Having a prototype from two tothissix Investing some two to six weeks. Investing some of time weeks. from one physical prototype iteration is, in and of itself, sufficient enable a constraint-driven design flow. system that allows you to specify all the of this time from one physical prototype rules for all such signals on your board is iteration is, in and of itself, sufficient to Physical Post Verify Fix/ Ship Prototype Layout in Lab important. Similarly, as the manufacturing Design Edit enable Sim a constraint-driven design flow. process for your designs evolves, you need a system that can combine such Figure 2: Design Building Differentiated Products Through Shorter, More Predictable Cyclessimulation is better than building physical prototypes—but the design cycle time is still unpredict Using post-layout new rules for both manufacturing and the rules for all such signals on your boardelectrical is important. Similarly, as theand manufacturing process for your designs domains guide the design Unpredictable evolves, you need a system that can combine such new rules for both manufacturing and electrical domains and as it an is iteration beingatdeveloped. an guide the design as it is being developed. Having the tail end of theHaving design cycle—either for lack of electrical rules adherence or for lack of manufacturing the the designdesign cycle long and, worse, iterationrule at adherence—makes the tail end of unpredictable. Figure 2. cycle—either for lack of electrical rules Develop constraints through simulation to enable a constraint-driven design flow. This involves using solution space Using post-layout adherence for lack of constraints, manufacturing exploration to ensure development of optimal constraints foror your design—these in turn, ensure that simulation is at better your product performs its peak in various operating conditions. This upfront investment helps avoid iterations at rule adherence—makes the design than building the tail end of the designphysical cycle, which could make it harder to predict when the design will be completed. cycle long and, prototypes—but the The cost of not developing such a constraint-driven design flow canworse, either leadunpredictable. to several physical prototype iterations design with debugging the lab cycleintime is or, worse, customers finding problems with your design. The cost of physical prototype varies among customers in different geographies; time lost in doing an iteration ranges from stilliterations unpredictable. two to six weeks. Investing some of this time from one physical prototype iteration is, in and of itself, sufficient to enable a constraint-driven design flow.

% of Nets Constrained Figure 3: With 50-75% of nets constrained on a dense, complex board, convergence is not guaranteed

Design

Post Layout Sim

Fix/ Edit

Physical Prototype

Verify in Lab

Figure 3. With 50-75% of nets constrained Many customers are being forced to use High Density Interconnect (HDI) technology to fanout small pin pitch onpin a pitches dense, complex BGAs. BGAs with of 0.8mm or lowerboard, usually require HDI build-up layers for fan out. A constraintdriven design flow must integrate HDI rules with electrical rules and traditional manufacturing convergence is manufacturing not guaranteed. Use a constraint-driven flow that supports HDI designs

Ship

rules together to ensure that the design is being built correct-by-construction. Checking for fabrication rules after the design has progressed to the very end only increases the number of iterations between the tail end the design process and doesn’t make the design cycle predictable. The solution is to use a constraint-driven flow that supports traditional manufacturing, electrical, and HDI manufacturing rules throughout the design flow. Figure 2: Using post-layout simulation is better than building physical prototypes—but the design cycle time is still unpredictable

Unpredictable

www.cadence.com

TECH REPORT The solution is to use a constraint specification system that is extensible in a manner that allows you to add your own rules. Such rules can be built on basic predicates—fundamental, atomic-level operations on objects within your designs—to allow you to customize your rules. Such rules, in most cases, can be checked as the design is modified— either interactively or automatically in batch mode.

Use a Constraint-driven Flow that supports HDI designs

Many customers are being forced to use High Density Interconnect (HDI ) technology to fanout small pin pitch BGAs. BGAs with pin pitches of 0.8mm or lower usually require HDI build-up layers for fan out. A constraint- driven design Building Differentiated Products Through Shorter, More Predictable Design Cycles flow must integrate HDI manufacturing Benefits of Deploying a Comprehensive Extend your constraint specification and management system rules with electrical rules and traditional Use of interfaces has increased in recent years Design and several communities have benefited from it. Semiconductor Constraint-driven Flow: manufacturing rules together to ensurecompanies reduce the risk of developing a new interface approach that may not be adopted widely. Systems companies benefit by having multiple sources for their devices that support an interface that is an industry • Improved product performance and chances of firstthat the design is being built correct-by-standard. Often, the timing of introduction of a new standard like PCI Express Gen3 doesn’t coincide with the introduction of the EDA tools that support constraints required by such new standards. pass success through optimum constraints. Optimum construction. Checking for fabrication The solution is to use a constraint specification system that is extensible in a manner that allows you to add your arepredicates—fundamental, developed through rules after the design has progressed toown rules. Suchconstraints rules can be built on basic atomic-levelexplorative operations on objects within e Design Cycles your designs—to allow you to customize your rules. Such rules, in most cases, can be checked as the design is simulation. Upfront development of such constraints the very end only increases the numbermodified—either interactively or automatically in batch mode. enables and drives the constraint-driven design flow. igns of iterations between the tail end of the

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design process and doesn’t make the design cycle predictable. The solution is to use a constraint-driven flow that supports traditional manufacturing, electrical, and HDI manufacturing rules throughout the design flow.

Develop ConstraintConstraints Driven PCB Layout

Post • Reduces time-consuming post-layout simulation Fix/ Physical Verify Ship Layout Edit Prototype in Lab Sim verification step. With simulationto a post-layout developed constraints that drive the constraintdriven thePCB post-layout simulation step now Figure 4:flow, Contraint-driven design makes design cycles predictable and shorter Benefits of deploying a comprehensive constraint-driven design flow: This shortens the becomes a post-layout verification. • Improved product performance and chances of first-pass success through optimum constraints. Optimum constraints time required to get the design to manufacturing. are developed through explorative simulation. Upfront development of such constraints enables and drives the constraint-driven design flow.

Extend Your Constraint Specification and Management System

• Eliminates unnecessary physical prototype iterations. This shortens design cycle time and reduces product Eliminates unnecessary physical prototype iterations. development This shortens design cyclecosts. time and reduces product

• Reduces time-consuming post-layout simulation to a post-layout verification step. With simulation-developed constraints that drive the constraint-driven flow, the post-layout simulation step now becomes a post-layout verification. This shortens the time required to get the design to manufacturing. •

Use of interfaces has increased in development costs. • Design cycles become predictable. become predictable. recent years and several communities • Design cycles have benefited from it. Semiconductor companies reduce the risk of developing Non-CD Flows a new interface approach that may not Building Differentiated Products Through Shorter, More Predictable Design Cycles be adopted widely. Systems companies Extend your constraint specification and management system benefit by having multiple sources for their Use of interfaces has increased in recent years and several communities devices that support an inter face that is have benefited from it. Semiconductor companies reduce the risk of developing a new interface approach that may not be adopted widely. Systems an industry standard. Often, thedevices timing companies benefit by having multiple sources for their that support an interface that is an industry CD Flow standard. Often, the timing of introduction of a new standard like PCI Express Gen3 doesn’t coincide with the of introduction newconstraints standard likeby PCI introduction of the EDA tools of thata support required such new standards. Express Gen3 doesn’t coincide with the in a manner that allows you to add your The solution is to use a constraint specification system that is extensible own rules. Such rules can be built on basic predicates—fundamental, atomic-level operations on objects within % of Nets Constrained introduction of the EDA tools that support your designs—to allow you to customize your rules. Such rules, in most cases, can be checked as the design is modified—either interactively or automatically in batch mode. constraints required by such new standards. Design Cycle Time

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Figure 5. A constraint-driven flow makes design cycles predictable and reduces unnecessary physical prototype iterations.

Figure 5: A constraint-driven flow makes design cycles predictable and reduces unnecessary physical prototype iterations

Develop ConstraintConstraints Driven PCB Layout

Post Layout Sim

Fix/ Edit

Physical www.cadence.com Prototype

Verify in Lab

Ship

Figure 4. Constraint-driven PCB design makes design cycles predictable and shorter.

Figure 4: Contraint-driven PCB design makes design cycles predictable and shorter

Benefits of deploying a comprehensive constraint-driven design flow: • Improved product performance and chances of first-pass success through optimum constraints. Optimum constraints 3 are developed through explorative simulation. Upfront development of such constraints enables and drives the

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Accelerated Design Authoring

Innovation in the design authoring space now allows engineers to author designs using multiple styles—tablebased for large-pincount devices, schematics for traditional circuits with small-pincount devices.

Design authoring has traditionally been associated with creating schematics in the EDA world. Additionally, in many instances the schematics created for simulation tend to be different than the ones used for driving the PCB layout process. Innovation in design authoring in recent years allows system designers to avoid having to author designs the same way engineers created them in the 1980s. Design architectures have evolved since the 1980s from a common clock architecture to one that uses source synchronous interfaces (DDR3/4) and serial links (PCI Express, SATA). At the same time, with larger scale integration possible with each new advanced IC node, many FPGAs and ASSPs have far more pins than ever imagined— devices with greater than 1000 pins are becoming commonplace. Adding these large-pin-count devices on a PCB requires them to be added as a symbol in the schematics. Schematics often use company-defined sheet sizes. Fitting a 750-pin or even a 500-pin symbol is impossible in the standard sheet. Engineers and librarians are forced to represent such large-pin-count devices as multiple split symbols with labels to specify connectivity. Such split symbols are totally useless on the schematics. Innovation in the design authoring space now allows engineers to author designs using multiple styles—tablebased for large-pin-count devices, schematics for traditional circuits with small-pin-count devices. Such

approaches can shorten the design authoring time significantly—in case of backplane designs, anywhere from 10X – 20X faster than traditional schematic creation. Time to create designs with large-pin-count devices (FPGAs or ASSPs or ASICs) mixed in with traditional circuits can be accelerated anywhere between 2X – 5X, depending on the number and size of large-pin-count devices. Use the right design authoring tool to shorten your design cycle. For mixed-signal designs or for purely analog / RF designs, often engineers use two different schematic tools: one for simulation and another for production PCB flow. This implies someone is recreating the schematics for production PCB flow. Improvements in integration between design authoring tools and simulation tools—single schematicdriven design authoring and simulation— allow engineers to avoid wasting time to recreate schematics. For RF circuits on a mixed-signal design, engineers can use a layout-driven design approach to create schematics based on the changes made to the etch elements in the layout. This eliminates the need to edit schematics manually to synchronize it with layout.

Design for Reuse A commonly used approach to shorten the design cycle is to reuse subsets of previous designs in new designs. Often, the next revision of a product is some modification that either reduces cost or adds some features that couldn’t be added with an earlier version—this is evolution of a product, not reuse of a

TECH REPORT subset of the design. For products that don’t fall into the evolution category, authoring the design in a manner that partitions functionality in a reusable manner can shorten the design cycle for other products. In such cases, the motivation to invest the time to partition and author designs for reuse has to come from upper management since the product team is usually focused on getting “their” product out the door quickly. When a product has several design engineers working in parallel, such partitioning becomes a necessity and can be leveraged to create reusable blocks. Reuse can also be applied to the physical layout of the partitioned subset of the design. In such cases, it’s important to have a relationship between partitioned logic and its physical implementation. While the physical layout is tied to a specific layer stack-up, reusing the placement and etch should be easy. This reuse is referred to as a reusable block. Reusable blocks also have to deal with constraints that are embedded in the design and were used to guide the physical implementation. Such constraints can be very useful for the design engineer who uses a reusable block designed by another engineer. Engineers reusing such blocks should also carefully analyze the constraints on standard interfaces to see if any exceptions were made to the constraints to make that board work. In other words, if design-specific changes were made to make the block work in its original design, make sure that those exceptions will not create any issues in your new target design.

FPGA-PCB Co-design FPGAs have grown in popularity over the years as their capacity and capabilities have increased significantly, while the cost-per-million equivalent system gates is going down with each new IC node. There are two categories of use for FPGAs: one is using FPGAs on end product PCBs; second is the use of FPGAs for ASIC prototyping boards. For both of these use models, integrating FPGAs on PCBs is a time-consuming effort. The first step in this process traditionally has been manual pin assignment using either the FPGA vendor tools (such as those from Xilinx or Altera), or inhouse developed spreadsheet-based approaches. Once the pin assignment is done, integration with schematic is done manually. Pin assignment and integration is done one FPGA at a time, without much feedback from any tools on the quality of pin-assignment results from routing the FPGA-on-board perspective. You can also use an integrated FPGAPCB co-design approach that brings PCB routing challenges into the pin assignment decision-making process. This automated approach should be done in accordance with the FPGA vendor’s pin assignment rules that optimizes the resource utilization of the FPGAs while improving the routability of FPGAs on board. This approach will reduce the number of frustrating iterations between PCB layout designer and FPGA engineer late in the design cycle Once the pin assignment is done, the integration of FPGA symbols in

There are two categories of use for FPGAs: one is using FPGAs on end product PCBs; second is the use of FPGAs for ASIC prototyping boards.

Modern Printed Circuits

schematics should be automated to reduce the time to integrate and avoid making any manual integration errors.

As the design complexities increase and design schedules shrink, one of the ways to shorten design cycle time is to partition the board among multiple PCB designers.

Divide and Conquer—Team Design Divide and conquer approaches can be applied on both initial designauthoring stage as well as during the physical implementation— place and route—stages.

Team Design During Design Authoring While having a team of engineers work in parallel shortens the design cycle, it also adds some design and process management challenges. Engineers working in a team while authoring the design have to deal with global signals and signals that interface to logic /circuit that is being designed by their colleagues. In such cases, using a signal-naming convention that is well understood and adhered to by all team members is important to avoid creating a problem that will only be caught during postlayout simulation or, worse, in debug stage in the lab with a physical prototype. Another area to manage is when each engineer embeds constraints on nets in their designs. When the constraints are added to nets that are local in scope, things should work fine. Once constraints are added or modified on signals that interface with other engineers’ blocks, there has to be some level of management on who has the ownership to make such changes. Often a system being designed has more than one fabric— either a combination

of internally developed ASICs on a PCB or a system of multiple boards connected via a backplane or through cables. In such cases, managing interfaces that cross the fabric boundary has issues similar to the ones when multiple engineers work on a subset of the design targeted for one fabric— PCB or a system in a package (SiP).

Team Design During Physical Implementation As the design complexities increase and design schedules shrink, one of the ways to shorten design cycle time is to partition the board among multiple PCB designers. This partitioning can be done vertically or horizontally. There are pros and cons of using one partitioning method versus another. It is important that the design system allows you to manage the partitions and synchronization between the partitions automatically without slowing down your system or requiring IT support to enable partitioning.

Productivity and Ease of Use Improvements This is an area that is common to all EDA tools. With every release of the software, there are improvements that help designers to be more productive. Productivity comes in many forms. The simplest involves automating some of the manual tasks. This applies to all areas of the tools. Earlier in the paper, we discussed one of the most fundamental productivity improvement capabilities— constraint-driven design. Included below are some examples of

TECH REPORT productivity improvements that shorten the design cycle and make it predictable.

Easy-to-use Intuitive Tools Help Dhorten the Time to Create Designs While this is very intuitive and selfexplanatory, software products tend to lose their “ease of use” moniker as they evolve over a period of time. Often software that is very easy to use doesn’t scale well for larger, more complex design challenges. Software that is very flexible may be difficult to use. This is an area that needs to be addressed with every release of the software you adopt. Success also requires providing feedback to your vendor on an ongoing basis—not once a year—to help them incorporate improvements that make your design experience better. A simple example of ease-of-use improvement is the ability to put vias with a single click for designs with hybrid HDI designs (HDI layers on each side of a non-HDI core). With traditional through-hole vias on a design, single click to place a via is the norm. With HDI layers around a nonHDI core, a system should allow users to instantiate multiple vias that are placed according to the rule specified with the user specifying the from to layer. This is a good example of how layout of HDI designs can be made easy even with a complex set of rules for advanced designs. Incorporating such new approaches allows users to shorten the time required to create their designs.

Auto-interactive Routing Technology Decreasing pin pitches, greater numbers of large pin count devices, and the need to reduce the footprint all contribute to the increased challenges in planning and routing a dense PCB design. Additionally, as the PCB interconnect paradigm shifts to increased use of standardized sourcesynchronous interfaces (such as DDR3/ DDR4) and serial interfaces (such as PCI Express), the number of constraints that must be adhered to increases. An example of a set of routing requirements for DDR3/4 interface is listed below. Data bus requirements: • Group and route data, data mask, and data strobe signals by byte lane • Tightly match members inside of the byte lane » 20 mils between members » 5 mils differential pair phase tolerance » It is not required to match lengths across all byte lanes. Length matching is only required within each byte lane. • Byte lane members should be routed on the same layer and only use vias to escape from surface mount devices so routing can be done on an internal layer

Address / Command / Control Bus Requirements: • Should be matched within +/- 10 mils • Routing on the same layer is not required but referencing the same

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plane layer is preferred If vias are required for multilayer routing, use the same number of vias (via matching) between each of the members Memory interface general requirements: • Signal ended impedance target: 50 – 60Ohms • Differential pair impedance target: 100 – 120Ohms • All routing should be routed close to and have a solid reference plane to provide a low-impedance path for return currents • To avoid any possible crosstalk between layers, develop a stack-up to utilize strip-line construction (reference plane above and below signal layer) instead of dual strip-line construction (two signal layers between reference planes)

Traditional automatic routers have been unable to route such dense PCBs with high-speed interfaces that require strict adherence to constraints (often derived through simulation for optimum performance on the PCB). To reduce the time to design such boards, you should do auto-interactive routing to not only capture, but adhere to, routing intent for dense designs with highly constrained, standards-based interfaces. After capturing design intent, use feedback from the tools on such planning to adjust your routing approach.

Accelerated Timing Closure

As the data rates increase and supply voltages decrease in today’s advanced interfaces, PCB designers spend more time to ensure signals in an interface meet timing requirements. With density on PCBs, the effort Building Differentiated Products Through Shorter, More Predictable Design increasing Cycles to get to timing closure— ensuring all signals meet timing requirements— can increase significantly.

Figure 6: Reduce layer counts and shorten design cycle through design planning Figure 6. Reduce layer counts and shorten Accelerated timing through closure design cycle design planning.

As the data rates increase and supply voltages decrease in today’s advanced interfaces, PCB designers spend more time to ensure signals in an interface meet timing requirements. With increasing density on PCBs, the effort to get to timing closure—ensuring all signals meet timing requirements—can increase significantly. To meet this increasingly complex challenge, you need an environment that allows you to graphically see real-time delay and phase information directly on the routing canvas – timing vision. Traditionally, evaluating current status of timing/length of a routed interface requires numerous trips to the constraint manager and as well as reviews of other current properties. What would be helpful here is a system to evaluate complex timing constraints and interdependencies amongst signals that show the current status of a set of routed signals—a DDRx byte lane or a complete DDRx interface. Ideally, you’d have information that defines the delay problem in the simplest terms possible.

To meet this increasingly complex challenge, you need an environment that allows you to graphically see real-time delay and phase information directly on the routing canvas – timing vision. Traditionally, evaluating current status of timing /length of a routed interface requires numerous trips to the constraint manager and as well as reviews of other current properties. What would be helpful here is a system to evaluate complex timing constraints and interdependencies amongst signals that show the current status of a set of routed signals—a DDRx byte lane or a

TECH REPORT Building Differentiated Products Through Shorter, More Predictable Design Cycles

complete DDRx interface. Ideally, you’d have information that defines the delay problem in the simplest terms possible.

• Solution space exploration (multiple concurrent simulations) for signal integrity analysis of digital signals

• Parametric Monte Carlo Additionally, you need a way to leverage analysis for analog signals the feedback from the system to tune • Batch design rules check differential pairs and meet timing constraints on byte lanes as well as Predictable and Reliable control and address bits, preferably in a Release Schedule way that reduces the manual one through Having a predictable and reliable new tuning and adjusting. Ideally, you’d drive release schedule from your vendor the strategy and execution, but have allows you to plan adoption of such the computer do the bulk of the work to releases based on the value of the meet complex timing constraints. Such an improvements promised. Migrating to auto-interactive strategy can allow you a new release can be time-consuming, to tune advanced interfaces like DDRx in especially if you leveraged the ability significantly less time compared to using Figure 6: Reduce layer counts and shortento design cycle through designtools planning extend the base either through traditional, more manual methods. in-house developed extensions or Accelerated timing closure by using third- party tools. An open As the data rates increase and supply voltages decrease in today’s advanced interfaces, PCB designers spend more Multi-core CPUs or Multi-CPU Machines architecture software platform time to ensure signals in an interface meet timing requirements. With increasing density on PCBs, the that effort to get Most personal computers these days come to timing closure—ensuring all signals meet timing requirements—can increase significantly. works in conjunction with third parties with dual cores. Engineering workstations works best quickly newsee releases To meet this increasingly complex challenge, you need an environment thatto allows you toadopt graphically real-time tend to have more cores in one CPU. Server delay and phase information directly on the routing canvas –that timing vision. Traditionally, evaluating status have productivity, ease ofcurrent use, and of timing/length of a routed interface requires numerous trips to the constraint manager and as well as reviews farms have been around for quite a while other critical capabilities implemented. of other current properties. What would be helpful here is a system to evaluate complex timing constraints and where many machines are linked in a interdependencies amongst signals that show the current status of a set of routed signals—a DDRx byte lane or for compute-intensive tasks. In anetwork complete DDRx interface. Ideally, you’d have information that defines theConquer delay problem in the simplest terms Divide and II—Outsourcing possible. either case, there are several applications Over the years, many companies have that can benefit Additionally, you needfrom a wayleveraging to leverage the feedback from the system to tune differential pairs and meet timing outsourced PCB layout partially or constraints byte lanes as well as control address bits, preferably in a way that reduces the manual one multiple on CPUs—whether they areand housed completely tobut service bureaus. through tuning and adjusting. Ideally, you’d drive the strategy and execution, have the computerMany do the bulk inside one computer or in multiple of the work to meet complex timing constraints. Such an auto-interactive strategy can allow have you toopened tune advanced larger global companies computers. These applications include: interfaces like DDRx in significantly less time compared to using traditional, more manual methods.

Having a predictable and reliable new release schedule from your vendor allows you to plan adoption of such releases based on the value of the improvements promised.

Figure 7. An example of how visual feedback on the design canvas avoids back-and-forth trips to the constraint manager.

Figure 7: An example of how visual feedback on the design canvas avoids back-and-forth trips to the constraint manager.

www.cadence.com

Modern Printed Circuits

design centers in low-cost geographies like India and China. Such companies hope to get two days’ work done in one due to time differences. Outsourcing opens up a new set of collaboration challenges for companies. In such cases communicating complete design intent is necessary. Complete design intent implies not just traditional connectivity (parts and how they are connected) but also the constraints that these parts and signals need to adhere to. Without communicating constraints, the design cycle becomes long, arduous and, worse, very expensive. The whole reason for outsourcing may be a wash if constraints are not embedded in the design. Once the layout is completed and sent back for review and approval, two approaches need to be taken. First, verify if any of the constraints were modified for any reason (compromises have to be made: which ones were made and are you ok with it?). Second, do post-layout verification to ensure that the realized physical implementation will work within the boundaries that are acceptable to you.

Use an Open Architecture An open architecture offers freedom to choose third-party tools. All vendors will claim to have an open architecture. Often you don’t find out how open the architecture is until it is too late. There are two ways that an open architecture helps shorten the design cycle.

The first is easy access to your design data for internal consumption or for use with third-party tools. Is your design data stored in a binary or an ASCII database? Is there a way for you to extract the information easily from the binary format without having to write any software? How easy is it for third parties to integrate their tools to your design data in the primary vendor’s format? Having a way to extract the information you need for internal use— documentation, reports, etc.— can be very helpful and can shorten the time it takes on each project significantly. Many tools offer report generation, some are customizable. Being able to create your own quickly as the need arises helps you focus on your project /design instead of struggling with the tools and tool vendors. The second way that an open architecture can shorten the design cycle is through tool extensibility for home- grown extensions. Does the tool allow you to customize the presentation layer (GUI, menus, etc.)? Does it allow you to add-in your extensions, whether they be for report generation or for a more serious application to fill in the gap while the vendor is catching up to your need? Being able to extend the system is important. In addition, the support for such extensions should not be consistent from release to release for 5-10-12 years. Such extensions should work with all the vendors’ tools—i.e. not have discontinuity as you move up to working with advanced designs, projects with advanced tools.

TECH REPORT SUMMARY In today’s environment, with increasing design complexity and continuous pressure to reduce the time to author and implement a design, you need to deploy all possible techniques and tricks to build a differentiated product quickly. At a minimum, you need to use a constraint-driven design flow in an open environment that avoids unnecessary design iterations or recreation of schematics, and allows teams to work effectively. New innovations like multistyle design authoring, global planning and routing, and FPGA-PCB co-design enable teams to create differentiated products much faster than possible with traditional approaches. Users of these technologies have reported design cycle reductions of up to 40%.

Having a way to extract the information you need for internal use—documentation, reports, etc.—can be very helpful and can shorten the time it takes on each project significantly.

MYLINK

Application Note:

Modern PrintedWorkplace Circuits Safety in Hazardous Locations Enhancing with PICO® 259-UL913 and 305 Series Intrinsic Safety Fuses

Challenge

atmospheres. For Class II and III hazardous locations, one of the greatest areas of concern is the apparatus surface temperature, which may trigger an explosion if the temperature is higher than the ignition point of the combustible dusts. For example, if the surface temperature of the apparatus does not exceed 120°C (under normal operating conditions) and 165°C (under fault conditions), a device is considered safe from a thermal ignition standpoint because it is not capable of causing ignition due to high surface temperature.

Circuit Protection Components from Littelfuse Meet Stringent Safety Standards

stible gases, vapors, and airborne dusts tend, by ry nature, to be explosive if present in the right trations along with sources of sparks or excess heat. e years, these hazards have led to some catastrophic of life and property. In response to this hazardous al, regulatory bodies around the world, including writers Laboratories, Inc., have worked to establish and standard that will minimize the hazards associated with al equipment for use in these environments. UL 913, was originally issued in 1971, is a U.S. national standard rinsically Safe Apparatus and Associated Apparatus in Class I, II, and III, Division 1, Hazardous (Classified) ns.”

pose of this standard is to specify requirements for struction and testing of electrical apparatus, or parts apparatus, having circuits that are not capable of ignition in Division 1 Hazardous (Classified) Locations ned in Article 500 of the National Electrical Code, ANSI/ 0. Limiting sources of electrical spark energy and high temperatures and maintaining separation distances are ects of the UL 913 standard.

rdous Locations and Intrinsic y Overview

cally safe apparatus have been developed to prevent al equipment from becoming sources of ignition of ve atmospheres in two ways:

gy limitation – To limit the spark energy

erature limitation – To limit the surface temperature

ss I hazardous locations, flammable gases or vapors can ed by sparks caused by electronic switching or arcing or surface temperature of parts exposed to the explosive

Applica

Enhanc

with PICO

Today, the installation, use, and maintenance of devices within potentially explosive areas requires that theses devices be certified to provide protection against ignition. Intrinsic Safety (IS) is a practical method of achieving such protection. Figures 1 and 2 show examples of common intrinsic safety systems.

Typical Hazardous Area Applications in which the UL 913 Standard Applies Almost every industry related to energy or basic materials production has potentially hazardous locations, such as: • Energy production: Oil/gas production/refining/storage/ The Challenge transportation, mining, etc. ® PICO 305 Series and 259-UL913 Series Fuses from Littelfuse.

Combustible gases, vapors, and airborne dusts tend • Materials processing: Chemicals manufacturing, their very nature, semiconductor fabrication, tank farms, etc.to be explosive if present in the rig concentrations along with sources of sparks or exce Over the years, these hazards have led to some cat Table 1. UL 913 hazardous locations losses of life and property. In response to this hazar Category of Hazard Degree of Hazard potential, regulatory bodies around the world, includ Class I: Location with flammable Division 1: Underwriters Laboratories, Inc., have worked to est gases or vapors Ignitable concentration of the hazards asso refine a standard that will minimize flammable gases, vapors, or environments. electrical equipment for use in these Class II: Location with combustible liquids can exist all the time dusts which was issued or originally some of the time in 1971, is a U.S. nation for “Intrinsically Safe Apparatus and Associated Ap Class III: Location with ignitable for Use in Class I, II, and III, Division 1, Hazardous (C fibers or flyings

ation Note:

EEWeb FEATURE

esigners and marketing executives are easily recognizable as the common faces of the

electronic components industry, but there are certainly many other aspects of a successful company’s operation that go into creating a truly leading presence in the market. The standards and certification process, admittedly

cing Workplace Safetynot in exactly Hazardous Locations the most prestigious or

O® 259-UL913 and 305 Series Intrinsic Safety Fuses

d, by ght ess heat. tastrophic rdous ding tablish and ociated with . UL 913, nal standard pparatus Classified)

celebrated of the bunch, always looms as a critically serious but easily neglected part of the work of any components manufacturer. Luckily these days, there are dedicated specialists, people like Saad Lambaz of Littelfuse, Inc., working hard to ensure that standards are not only met well in advance but that the best possible requirements are in place and working as they should.

The essential task is not only to make sure that a design does what it is designed to do, but also that the design meets the standards that exist outside those applicationspecific requirements.

Although it may seem like a secondary consideration, in reality it stands as

atmospheres. For Class II and III hazardous locations, one of the requisite, and makes greatest areas a of fundamental concern is the apparatus surface temperature, which may trigger an explosion if the temperature is higher than the difference between the industry’s the ignition point of the combustible dusts. For example, if the surface temperature of the apparatus does not exceed 120°C followers and its leaders. (under normal operating conditions) and 165°C (under fault conditions), a device is considered safe from a thermal ignition standpoint because it is not capable of causing ignition due to high surface temperature. Today, the installation, use, and maintenance of devices within potentially explosive areas requires that theses devices be certified to provide protection against ignition. Intrinsic Safety (IS) is a practical method of achieving such protection. Figures

ast, apparatus manufacturers have traditionally been forced o send fuses to a third-party supplier or create their own Modern Printed Circuits econdary process to encapsulate the entire fuse to meet the equirements of the UL 913 standard. Now, the PICO® 259L913 and PICO® 305 Series can help reduce total product Intrinsically Safe Products ost. These sealed fuses, available with ratings ranging from Having begun Fuses his efforts Require Intrinsically Safe 2mA to 5A, and ratings up to 750mA, respectively, are working for Underwriters Laboratories eal for applications in the oil, gas, mining, chemical, and (UL), a familiar Within a hazardous area, a ubiquitous variety of electronic devices and safety harmaceutical industries because they are designed tocertification operate (Figure 3) are often used for production or maintenance plays a central within environments where therecompany is dangerthat of explosion from role activities. in required third-party certification aulty circuits. In addition to UL 913 certification, these fuses processesand any legitimate supplier, meet ATEX (EN 60079-0 EN 60079-11) (IEC These types of & products include:for IECEx Lambaz now uses his skills to represent 0079-0 & IEC60079-11) requirements. • Motor controllers Littelfuse, one of the biggest companies in the modern components game, as • Lighting Global Standards Manager for the company’s Electronics Business Unit. As • Communication handsets a representative to a number of industry • Flow meters committees and technical groups, he also diligently to help ensure that the • Process control and works automation electronics industry’s biggest players are • Sensors working as hard as possible to uphold industry standards to the highest degree. To use this type of apparatus safely in a hazardous location, the available energy must be limited to avoid igniting explosive As Lambaz explains, the essential task materials in the environment. An intrinsically safe certified is not only to make sure that a design fuse is useful in limiting the current under abnormal conditions ® 305 Series and 259-UL913 does what it is designed to do, but also gure 4. PICO Series Fuses generating from to ensure that the circuit will open without a ttelfuse. that the design meets the standards that spark capable of causing ignition. Arcing can occur when exist outside those application-specific fuse opens, which must be contained within the fuse’s ® 259-UL913 he PICOthe (green colored) fuse design requirements. Withand thisits specialized encapsulation. Thesuitable surfacefor temperature of the fuse also must ncapsulation (Figure 5) are use in intrinsically knowledge at his disposal, Lambaz makes be kept the temperature that could ignite explosive afe apparatus andbelow associated apparatus for applications with gases or dust. ® oltages up to 125Vrms (190V peak). The PICO 305 Series

orange colored) fuse is rated for applications up to 277V. The use’s encapsulation is >1mm thick and thus eliminates the eed for an added encapsulation process or conformal coating f the PCB where the fuse is placed. The fuse encapsulation mits the temperature and energy that is exposed to the azardous environment and prevents particles from entering he fuse body.

PICO® 259-UL913 and 305 Series Intri

Intrinsic safety standards increase overall sa apparatus, which increases the level it possible for Littelfuse to essentially put of prote in these hazardous operating environments. their products fully to the test against the

industry’s standards, long before sending them Designing off for official review. “StandardsSafe Cir Intrinsically ® can bePICO intimidating, especially when 259-UL913 and it305 Serie comes to new areas and when trying to Intrinsically Safe Products ® 259-UL913 Both theproduct. PICO and PICO® 305 design a new It can be tough Require Intrinsically Safe Fuses Safe Fuses from Littelfuse (Figure 4) are en to manage the path through the many approved under the aUL 913 standard for Intr different Within a standards hazardous and area,specifications,” variety of electronic de Electrical Equipment to operate he says. Butare still, he adds, theproduction ability toin hazardous (Figure 3) often used for or mainte series fuses, rated at 125V and 277V re activities. do so two completely and effectively makes fuses sold that worked are certified all theonly difference. Having for anto meet thi These types of products include: past, manufacturers have tradition agency thatapparatus is responsible for numerous to send fuses to a third-party supplier or cre standards, especially in North America, , • Motor controllers secondary process to to encapsulate it’s much easier for Lambaz know howthe entire • Lighting of theinUL standard. Now, thingsrequirements are going to work the913 big-picture ® UL913 and PICO 305 Series can help redu scheme of the standards certification • Communication handsets cost. These sealed fuses, available process, and this, he implies, is the kind ofwith ratin 62mA to 5A,toand ratings up to 750mA, resp • Flow meters expertise needed effectively provide ideal for applications in the oil, gas, mining, c for any company’s long-term success. • Process control and automation

pharmaceutical industries because they are within environments where • Sensors Additionally, Lambaz points out, “athere big is danger faulty circuits. In addition to UL certifica part of my is to an active part in of913 To use thisjob type of be apparatus safely a hazardous meet ATEXand (ENtechnical 60079-0groups & EN 60079-11) an the thecommittees available energy must be limited to avoid igniti 60079-0 & IEC60079-11) requirements. that set these standards, too, and to materials in the environment. An intrinsically safe fuse is useful in limiting the current under abnorm to ensure that the circuit will open without genera spark capable of causing ignition. Arcing can occu the fuse opens, which must be contained within t encapsulation. The surface temperature of the fus be kept below the temperature that could ignite ex gases or dust.

Normal Fuse (used non-hazardous Figure 4. PICO® in 305 Series and 259-UL913 Se environments) Littelfuse.

The PICO 259-UL913 (green colored) fuse Figure 5. The >1mm-thick encaps encapsulation (Figure 5) are suitable for use Series fuses and keeps them sealed, safe apparatus associated apparatus for temperature exposed to the exp voltages up to 125Vrms (190V peak). The PI (orange colored) fuseItisalso rated prevents for applicationg fuse operation. fuse’s encapsulation is >1mm thick and thus entering the fuse body, which m Figure 3. A variety of electronic products are design

Figure variety of electronic products are designed for safelocations. A variety3.ofAelectronic productrs are designed for safe use in hazardous use in hazardous locations.

Another aspect of intrinsic safety is the necessity of preventing the temperature of a component inside apparatus such 22 as gauges, meters, and valves from rising to an unsafe

insic Safety Fuses

EEWeb FEATURE Outdoor LED Lighting

Application Note:

afety of the Enhancing Workplace Safety in Hazardous Locations with ection of human lifefrom the roots of the matter understand possible to meet the requirements of ® 259-UL913 and 305 Series Intrinsic Safety Fuses PICO . where the requirements come from and different or competing policies. But,

what they really mean to the market.” with a wise sense of experience and anticipation, Lambaz feels that there rcuitsPerhaps with unsurprisingly, standards from different parts of the multifaceted is always room for improvement. es Fuses global market are often in conflict with increase overall safety of the Intrinsic safety standards 5 Series one Intrinsically another, andapparatus, attempting to comb live a global world,” Lambaz which increases the“We level of in protection of human life ncapsulated fuses through the dense catalogs of standards reflects, “so it’s becoming increasingly in these hazardous operating environments. rinsic Safety of uncommon for bigger companies to evices can be an intimidating task for someone s locations. These “Trying to design a settle forCircuits simply targeting enance out of their depth. Designing Intrinsically Safe withone national espectively, are the product that hasPICO to meet very different or continental market. The global ® 259-UL913 and 305 Series Fuses is standard. In the requirements is a huge challenge, and aspect [of the modern market] makes ® 259-UL913 and PICO ® 305 Series Intrinsically nally been forced Both the PICO more often than not, the process will it essential to understand the nature eate their own Safe Fuses from Littelfuse (Figure 4) are encapsulated result in more than one product.” But, he of standards throughoutfuses the whole e fuse tointerjects, meet thethat’sapproved under the UL 913 standard for Intrinsic Safety of where the big-picture world, which is more an integrated ® 259the PICO Electrical Equipment to operate in hazardous locations. These challenge stands, and why Lambaz network than ever before.” In such uce totalconsiders product it the most two series fuses, rated at 125V 277V respectively, are the important duty for a and world, it only makes sense that ngs ranging from only fuses sold that are certified to meet this standard. In the those in his position to “make that a little developments in standards in one pectively, are to harmonize past,standards apparatusacross manufacturersplace have are traditionally beenfar-reaching forced easier, sure to have to he send fuses a third-party supplier or create their own chemical, theand board.” Today, says, theto standards effects throughout the whole global secondary process to encapsulate the entire fuse to meet the designed to operate organized and put forth by organizations network, whatever they may be, and requirements of the UL 913 standard. Now, the PICO® 259of explosion from such as the IEC, or the International the effect that these variables can ® product UL913 and PICO® 305 Series can help reduce total ation, these fuses Electrotechnical Commission, do a have only highlights the necessity of s location, cost. These sealed fuses, available with ratings ranging from nd IECEx (IEC solid job streamlining pretty things diligent work in increasingly essential ing explosive 62mA to 5A, and ratings up to 750mA, respectively, are and making it roles like those played by Mr. Lambaz. certifiedin the modern market ideal for applications in the oil, gas, mining, chemical, and mal conditions pharmaceutical industries because they are designed to operate ating a within environments where there is danger of explosion from ur when faulty circuits. In addition to UL 913 certification, these fuses the fuse’s meet ATEX (EN 60079-0 & EN 60079-11) and IECEx (IEC For more information on designing se also must 60079-0 & IEC60079-11) requirements. explosive PICO® 259-UL913 and PICO® 305

The global aspect [of the modern market] makes Outdoor LED Lighting it essential to understand Enhancing Workplace Safetytheinnature Hazardou of standards PICO 259-UL913 and 305 Series Intri throughout the whole world...

PICO 259-UL913 Intrinsically Safe Fuse ries Fuses from with Encapsulant

circuits u Series In Fuses, including detailed specs, ampere rati dimensions, etc., consult the 259-UL913 an datasheets available on the Littelfuse websi in choosing the right amperage PICO® 259305 Series fuse for the application, consult by-step guide, Fuseology: Fuse Characterist Consideration Factors.

e design and its sulant surrounding 259-UL913 e in intrinsically r limiting applicationsthe withenergy and Figure 4. PICO® 305 Series and 259-UL913 Series Fuses from plosive during ICO® 305atmosphere Series Littelfuse. ns up to 277V. The and fibers from gases, dusts, s eliminates the for use ® 259-UL913 (green colored) fuse design and its The PICO makes it ideal in hazardous

ned for safe

Modern Printed Circuits

In direct relation to Lambaz’s particular such a way that they are incapable of area of expertise at Littelfuse, the igniting combustible atmospheres, company offers some of the world’s requiring no other means of protection. current leading circuit protection components for use in hazardous Recently, Littelfuse introduced two locations (i.e., locations and areas fuses specifically for intrinsic safety where combustible concentrations needs in industrial applications, the of gases, vapors or dusts exist in PICO® 259-UL913 Series and the PICO® 305 Series. With these fuses, the typical normal operation) by utilizing the risks for an explosive ignition are “intrinsic safety” protection method. greatly reduced by a specially designed These intrinsically safe products and encapsulation layer that first, minimizes components, which are so named for the temperature of the fuse in both having advanced safety features for a normal and abnormal circumstances particular hazardous environment built and second, seals the fuse from the in to their systems, are not altered or fit surrounding combustible atmosphere. As into additional structures to make them Lambaz details, the company also prides safe but are rather designed for specific itself on being able to provide these energy-limiting and temperaturespecialized components in a complete limiting safety measures from the ground package, without requiring customers up. For example, some end-product to undertake any further steps to offer equipment may be built with or installed the product in its finished form, ready in extra-strong enclosures that use for use in intrinsically safe equipment. the “explosion-proof”/ “flame-proof” Outdoor LED Lighting protection method. In the case of an Application Note: LittelfuseSafety has a network of global explosion, these enclosures contain the Enhancing Workplace in Hazardous Locations with ® 259-UL913 and 305 Series Intrinsic Safety Fuses PICO resources, Lambaz points out, which blast and prevent the propagation of allows the company to combine these any flames outside of the enclosure’s usually separate steps into a complete boundaries. Intrinsically safe products, package that saves customers time on the other hand, are designed in Hazardous Area Intrinsically Safe Apparatus

Safe Area Zener Barrier

Power System L

Protected Circuits

N X1

Ground E

Intrinsic safety system using zener barrier

Figure 1. Intrinsic safety system using zener barrier.

Hazardous Area

Safe Area

• Food producti

• Others: Pharm manufacturing

EEWeb FEATURE and cost. Highlighting the company’s very common to see products up for pre-emptive attention to standards certification that had not met very and certification, he states that “our basic requirements,” Lambaz recalls. knowledge of the certification process “My advice is to take the time and learn also gives us the ability to ensure that as much as you can about standards no further testing is required and that that will be applicable to your product, Outdoor LED Lighting customers can expect the best possible long before it even reaches the thirdApplication Note: results from third-party certification.” party certification agency.” It’s that Enhancing Workplace Safety in Hazardous Locations with With few companies able to offer such kind of philosophy that puts Littelfuse PICO® 259-UL913 and 305 Series Intrinsic Safety Fuses ahead-of-the-curve service, Lambaz, with a step ahead of the competition. good reason, feels that this knowledge is what gives Littelfuse its edge. It’s safe to conclude that it can only be of great advantage for InHazardous understanding the role that a company to take the time to Area standards and certification play in the understand, as Lambaz says, “the Safe Area Intrinsically manufacturing and supply process, it’s different requirements of comparable Safe Apparatus Zener Barrier Power System easy to see that the knowledge of endstandards, their history, and any of product standards in their many forms the changes to the standards that L Protected and variations stands as something that can affect your products.” With Circuits is only slightly less fundamental than exactly that kindNof considerate the basic engineering knowledge that scope at their disposal, it seems X1 allows a company to build products in that it can only be short time before X the first place. These standards guide the rest of the industry has caught Ground design and manufacturing from its on to the demonstrated wisdom most basic stages, and, naturally, the that Littelfuse displays in working E success of a company’s innovations is to stay ahead of the constantly only truly measured by how well they evolving curve of standards and meet the requirements of the industry. certification with an understanding “At Underwriters Figure Laboratories, it safety was system of how much it really counts. 1. Intrinsic using zener barrier.

Littelfuse has a network of global resources, which allows the company to combine these usually separate steps into a complete package that saves customers time and cost.

Hazardous Area

Safe Area

Intrinsically Safe Fuse Intrinsically Safe Apparatus

Safety Barrier

Figure 2. Intrinsic safety system using galvanic isolator. Intrinsic safety system using galvanic isolator barrier

ion: Grain milling, baking, brewing, distilling, etc.

Basic Principles of Fuse Operation

maceutical manufacturing, cosmetics g, pumping stations (gas, oil, sewage, etc.)

When an abnormal condition (such as a capacitor failure, IC short, etc.) occurs in an electronic circuit, it creates an

Modern Printed Circuits

Breaking Out the

BGAs 26

EEWeb FEATURE

all grid array devices are, without question, an increasingly important aspect of printed circuit board design. While their benefits are numerous, they present the unique challenge of requiring an enormous amount of traces to originate in a small area underneath a device and then go all over the board without crossing traces. The most challenging aspect is getting those traces out from underneath the board, a process called creating a breakout or fanout. In the breakout, these traces are said to escape from underneath the board and come to the outside where they are more accessible. A poorly designed breakout can be overcome by increasing the layer count on a PCB but that increases the cost and complexity. There are number of different scenarios that would require different approaches to breaking out the traces, however, due to limitations in space, only the more common concepts and methods will be discussed here.

Modern Printed Circuits

Throughhole vias are simple and inexpensive and they allow you to get your signal to any layer on the board you need.

When approaching a BGA breakout, there are several key features to watch out for. Foremost is the pin count, or how many balls there are on the device. Equally important is the pitch between the different pins. As the pitch decreases, the space available to run traces starts disappearing and the approach both in the fanout and the types of vias changes. There are different patterns used as well that will affect how you break it out, whether the balls are in perfect grids, in an offset pattern, if the pattern is different for different portions of the component, and if there are no pins in the center of the component. Finally, not dependent on the component, is the constraints given to you by your manufacturer. If you need more demanding constraints, you may need to look at a different manufacturer but that will cost more and there is a limit where even the most advanced manufacturers simply cannot go smaller.

Blind vias allow you to connect an outer layer with an inner layer without having to go entirely through the board.

A key part of actually fanning out the signals is the use of vias. Through-hole vias are simple and inexpensive and they allow you to get your signal to any layer on the board you need. However, it also makes a hole all the way through all of the layers, so whether or not a via is attached to a certain layer, that spot on each layer is unusable. With this limitation, through-hole vias are really only feasible while working with BGAs up to a couple hundred pins. After that, it starts to become increasingly difficult until it is completely impossible to properly break out the BGA using through-hole vias with or without an astronomical number of layers. Blind and buried vias, while more expensive, greatly expands the capabilities of the board and allows for greater pin count while keeping the layer count reasonable. Blind vias allow you to connect an outer layer with an inner layer without having to go entirely through the board. Buried vias can connect two inner layers without affecting layers that are not between them. These free up a significant amount of space on the board and may save cost in the long run. Once it is time to actually start designing the board, look into how the pins are set up. If there are general purpose IO available throughout the component and it is possible to choose the IO closer to the edge, do so. It is much easier to break signals out of the corners and sides of the component versus the center, so a proper setup will make your life easier. Also, in general, components have more of their power and ground pins

EEWeb FEATURE It is much easier to break signals out of the corners and sides of the component versus the center, so a proper setup will make your life easier.

in the center, so providing appropriate ground and power planes simplify matters by allowing vias to be dropped down directly to the planes. You will not be able to utilize that center space, but at least the effort of getting those signals out will not be necessary. There are two very common techniques that are used to fanout the different signals on a BGA. The north- south-eastwest approach is very straightforward, easy to conceptualize, and works well with relatively small BGA components.

In essence, take the traces out the side of the component that theyâ&#x20AC;&#x2122;re closest to. A pin closest to the top of the component will have its escape trace go up toward the top. A pin closest to the left side of the component will go out that way. The other technique is the layer-biased approach, where all the signals on each layer tend to go a certain direction, either vertical or horizontal, until they are out from beneath the BGA. This is generally used with higher pin count devices that also require more layers to effectively route.

In essence, take the traces out the side of the component that theyâ&#x20AC;&#x2122;re closest to.

Modern Printed Circuits

Done properly, you can create a board that will be inexpensive, powerful, and well balanced electrically. Done improperly, it could cost significantly more than it needs to be, be larger than it needs to be, and have serious ramifications to the performance of high frequency signals. At the level of each pin, there are also two common ways to get the signal away from the pin itself. The dog-bone is so named because it looks like a dog bone. By creating a via away from the BGA pad, you decrease difficulties with soldering and can potentially increase spacing for the traces to be ran. The other common option is the via-in-pad, in which the via originates in the center of the BGA pad. This is useful as it doesnâ&#x20AC;&#x2122;t use any additional space on the outer layer, however, it presents solder wicking concerns and is thus discouraged by some manufacturers and assembly houses. When working on the design, it may be a good idea to contact your manufacturing chain and discuss with them their personal preference on the matter and see if the defect rate would make via-in-pad a non-viable option.

BGA breakouts is another step in the process of designing high quality circuit boards. Done properly, you can create a board that will be inexpensive, powerful, and well balanced electrically. Done improperly, it could cost significantly more than it needs to be, be larger than it needs to be, and have serious ramifications to the performance of high frequency signals. If delving into BGA design for the first time, it is recommended to find a mentor who can work with you and provide insight and feedback as well as looking deeper into written technical resources. The time and effort invested into learning how to do properly breakout a BGA will become even more valuable as time moves on and technology produces even smaller pitched, higher pin count components.

Advanced Assembly was founded to help engineers assemble their prototype and lowvolume PCB orders. Based on years of experience within the printed circuit board industry, Advanced Assembly developed a proprietary system to deliver consistent, machine surface mount technology (SMT) assembly in 1-5 days. Itâ&#x20AC;&#x2122;s our only focus. We take the hassle out of PCB assembly and make it easy, so you can spend time on other aspects of your design. 20100 E. 32nd Pkwy #225 | Aurora, CO 80011 | www.aapcb.com www.aapcb.com | 1-800-838-5650

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STENCIL Design

EEWeb FEATURE

hile it is possible to use the solder paste layer gerber file as the basis for a stencil with a standard thickness, the result will be acceptable, at best, and at worst, completely unusable. However, spending time to refine and improve the basic solder paste design, as well as choosing the thickness and material, will result in a stencil that will consistently provide successful results.

Modern Printed Circuits

By calculating how much paste will release on the terminations, versus how much will release on the ground pad, you can determine the correct opening size.

When designing stencil layouts, be careful to specify the solder mask thickness on the PCB fabrication drawings because the stencil has to print down below the mask to contact the pads. If the solder mask is too thick, the stencil will have contact problems. The stencil design provides an opening of determined size and the thickness of the stencil is representative of the amount of paste that will be applied. Squeegees used with stencils often will be metalpointed or wedge-shaped. Most stencils are used with semi-automatic printers, which provide the constant squeegee pressure and movement required for uniform results. The small apertures required by miniaturized components can push the limits of the area ratio rules, reducing them below the 0.66 threshold and reducing solder paste volume on the pad. Therefore, area ratios and transfer efficiency calculations are necessary, especially with small chip packages. You will need to calculate the paste lay down volume with small terminations area ratio with a 5 mil foil stencil. By calculating how much paste will release on the terminations, versus how much will release on the ground pad, you can determine the correct opening size. Aperture openings for other components

need to be enlarged if thinner stencil foils are used. You also need to calculate aperture size to maintain the same solder volumes and how much pad overflow that you will allow. New stencil design software can perform many different stencil design calculations and analyses. Area ratio and transfer efficiency (ARTE) can be used to find low flow areas, thus avoiding alignment issues. ARTE allows rapid changes of stencil design options, including changes in aperture size, shape or foil thickness, and predict lay down volumes of apertures. With ARTE software CAM imports, the stencil Gerber D file specifies a minimum area ratio threshold and selects a foil thickness. The software calculates the correct aperture volume and aspect ratio for each pad shape. The stencil design must account for PCB changes in size. On larger PCBs, final overall size can vary by up to .015 inches per 12 inches. In surface mount assembly, the stencil is required to deposit accurate and repeatable solder paste. The solder paste brick holds the components in place so that when reflowed, they are secured properly to the PCB. The stencil type, thickness and shape of its apertures will determine the size and position of the paste bricks, which is essential to ensuring a high-yield assembly process.

EEWeb FEATURE Design guide for stencil technology is determined by pad aspect ratio, which is defined as aperture width divided by stencil thickness and should be greater than 1.5. Aspect ratio is a usable guide. Aspect is the difference in surface friction forces that either allows paste to flow from an aperture and on to a pad or causes paste to be held within an aperture. These forces can be calculated and are referred to as the aspect ratio. With the introduction of BGAs and QFNs, the aspect ratio has shrunk and is defined as the area of the aperture opening divided by the area of aperture walls. The walls of the aperture are trying to hold the paste in the aperture, while the pad under the aperture opening tries to pull the paste away after the squeegee passes. If the aspect ratio is greater than 1.5 and the area ratio is greater than 0.66, you should have excellent print performance using a good quality laser stencil. During the printing process, as the stencil separates from the PCB pad, the surface tension forces determine whether the solder paste will stay on the pad or remain adhered to the stencil aperture walls. When the pad area is

greater than 66 percent of the aperture wall surface area, the surface tension on the pad will improve paste transfer. As the ratio decreases below 66 percent, paste retention efficiency on the pad decreases and print quality becomes erratic. It is recommended that finer pitch aperture openings be slightly smaller than the landing pad size. This is primarily for improved contact between the landing pad and the underside of the stencil, which prevents bridging on fine pitch component. Aperture width reductions must be taken equally from each side so that aperture is centered on the pad. While other technologies are being improved that have faster setup times for small prototyping, stencils are a well-established and well researched technology that can yield great results with great repeatability. With a proper design, rework will be kept to a minimum and boards are most likely to receive the right amount of solder in the right locations.

If the aspect ratio is greater than 1.5 and the area ratio is greater than 0.66, you should have excellent print performance using a good quality laser stencil.

Modern Printed Circuits

The BIG Advantage of SMALL GDTs New FLAT GDT Technology from Bourns Revolutionizes a Familiar Component Side-‐by-‐side Size Comparison

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Working hard to forge the protective components that can keep today’s emerging technologies working at their best, Riverside, California’s Bourns, Inc. can be found playing a trusted role in an impressive variety of the modern world’s essential applications. A leading manufacturer and supplier of a range of products such as sensors, circuit protection devices, magnetic components, and resistive parts, Bourns is notably relied on by an impressive range of markets that includes the automotive, industrial, consumer, communications, and medical industries. With a history that begins with founder Marlan Bourns’ personal contribution to the Manhattan Project and progresses with the Apollo space program into a new era of modern technology, Bourns has been doing some very impressive things behind the everyday scenes.

Modern Printed Circuits

Speaking with a panel of representatives from the Bourns Product Line Department, we learned a bit more about some of the recent work that the company has been doing in the circuit protection realm in particular. With a successful new line of aptly titled FLAT® gas discharge tubes (GDT) just released, we figured it was as good a time as any to find out what’s going on at Bourns, and we were certainly not disappointed. As with much of today’s taken-forgranted technological infrastructure, many of Bourns’ products serve essential functions in a rather esoteric fashion. To get us started, Product Line Manager Kurt Wattelet was kind enough to offer a succinct explanation and history of gas discharge tubes as a circuit protection technology. At first, he says, “the old air-gap protector from which the GDT was developed was a very coarse level of protection, easily influenced by environmental factors such as humidity.” Sometime in the 1960s, he says, the need for better protection became overwhelmingly clear to industry professionals. Soon, GDT

technology emerged to become a part of the quick-evolving revolution in circuit protection, along with silicon devices. In a basic sense, Wattelet describes GDT technology works by developing a potential between two electrodes in a gas-filled chamber, which, with the aid of some carbon striping to aid ignition, then arcs over at the set voltage threshold to protect the circuit. “As a result, you can get a wide range of voltages offered in GDTs designs from 90-volts up to 7.2kV,” he says. Also unique to each gas tube design is a necessary coating on the electrodes, which, Wattelet points out, “helps with ignition and extends the life of the device.” He explains that “each manufacturer has a personal ‘special sauce’ for their coatings,” which plays a big part in differentiating products. “The real driver for GDT protection was the telecommunications industry, which is why Bourns telephone line protection module products are comprised of our GDT devices. In the United States, if there is a copper telephone line, it likely has a Bourns GDT in it,” explains Wattelet.

EEWeb FEATURE More recently, gas tubes have found their way into the industrial and even medical fields, “where you need a very low-capacitance, low-leakage type of protection. Semiconductor devices tend to be more about precision,” Wattelet interjects, “though they also tend to be higher in capacitance with significantly less capability to handle large amounts of current.” To get the same current capabilities of GDTs, large silicon devices are required, and the team at Bourns knew there was a better way.

and space-restricted applications in telecommunications and industrial communications equipment, surge protective devices, and printed circuit board (PCB) assemblies.” According to specs, the new series delivers a rather remarkable 75% reduction in volume as compared to standard 8mm Bourns GDTs.

Johan Schleimann-Jensen, R&D Manager for the FLAT GDT Product Line, adds that the company’s new compact GDT series also offers, “superior surge current ratings, Very recently, the company has low leakage and insertion loss, and introduced a new GDT series using a constant capacitance regardless breakthrough flat package design. of voltage.” Optimized for longCharting new territory in both term reliability and performance, volume and space-saving design, the Bourns devices are imbued with two-electrode Bourns Model 2017 •  Unique isola4on “wrinkled creepage” pathway design allows the GDT ® GDT was, as company voltage limiting capabilities without Series FLAT to compressed axially representatives point forth •  Isola4ng pathway lengths are out, same put as conven4onal GDTs impacting signal or system operation. specifically to meet “the more sensitive detail, the Model 2017 Series is an •  This results in se[ng a new standard in space-‐saving cTo ircuit protection ITU K.12 Class III GDT device rated at protec4on design requirements of high-density 10 kA on an 8/20 μs waveform, and features DC breakdown voltages from 90 to 500 volts. The Bourns FLAT GDT also demonstrates an innovative variety of mounting

Unique/Patented Design Technique

According to specs, the new series delivers a rather remarkable 75% reduction in volume as compared to standard 8mm Bourns GDTs.

2017-xx-A-RPLF

FLAT® GDT Model 2017 kA Surge Arrestor with FLAT® Technology

2017-xx-SMH-RPLF

2017-xx-SMC-RPLF

Modern Printed Circuits

options, which include bottom-side PCB, horizontal, and vertical surface-mount versions, “as well as a leadless design for cartridge or clamp-fit scenarios.”

Bourns is now working with companies that, as he describes, “need to cut the circuit board size by half on a particular design, and therefore are looking seriously at the obvious benefits of our FLAT GDT. They are placing them on the top side of a PCB near a connector where you couldn’t normally get a standard GDT.” The company is also working on a three-electrode version of the FLAT GDT, which would essentially combine two tubes into a single device that shares a common, center electrode. Whether saving customers the added steps of modifying many of their products to allow for yesterday’s standard protection measures, or giving the modern infrastructures that define our modern everyday world the reliability that keeps life in motion, Bourns continues an admirable journey to providing the best protection a circuit can get.

ture for FLAT® GDT Technology Despite the obvious needs that Bourns addresses with the FLAT series, Wattelet makes it clear that a frontier of innovative applications is just opening up for the company’s leading designs. “Another key area is with solar inverters,” he says, highlighting “where companies that design these really small inverters that they place on each solar panel and combine at a central location.” Naturally, he concludes, “size is a big consideration here, and there is clearly a big interest in our reduced footprint.”

•  Product roadmap

4on

ustomers now rested in GDT for d applica4ons

ons

ns equipment e devices ols

•  Developing 3E (three electrode versions) combining two 2-‐electrode GDTs into a single device with three terminals

Likewise, Wattelet informs us, “The real estate on cell towers is becoming a big issue in the telecommunications world.”

The company’s new compact GDT series also offers superior surge current ratings, low leakage and insertion loss, and constant capacitance regardless of voltage.

downstreamtech.com

Modern Printed Circuits

PCB

Prototyping Made Easy

INDUSTRY INTERVIEW

Bay Area Circuits’ Unique Process Technology Gives Engineers the Full Package Having the competitive edge is paramount in today’s PCB manufacturing industry. With outsourcing becoming more and more cost-efficient for prototyping and assembly, American board shops are developing new, unique ways to keep the business in the US and offer significant value at a competitive cost. For Bay Area Circuits, this means

Interview with Stephen Garcia President of Bay Area Circuits

overhauling every step of the prototyping process—from design to manufacturing to assembly. EEWeb recently spoke with Stephen Garcia about the primary investments the company has made in equipment, proprietary software, and mechanized assembly—all of which add to the customer-focused approach that makes the outsourcing option obsolete.

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Could you give us a little background about yourself and Bay Area Circuits? My grandfather, Lawrence Nobriga, founded Bay Area Circuits in 1975 so I grew up in and around the business. After college I worked in the technology industry and about 6 years ago returned to take over the leadership of Bay Area Circuits where I’ve tried to apply many of the lessons learned working in a startup environment. Two years ago we relocated to a new facility in Fremont which doubled our capacity. I added a former colleague, Brian Paper, as our COO and Brian and I have worked closely on a variety of marketing, sales and operational efforts in support of our growth plan. This year, we’re proud to be celebrating our 40th year in business. Bay Area Circuits is a Silicon Valley-based PCB manufacturer that specializes in quick-turn prototypes and small- to midsized production runs. Over the last three years, we started to introduce design as well—we have in-house electrical engineer designers. In addition to that, we have added assembly services so that we can offer our customer base the full package, from design to manufacturing to assembly. With ever-shortening deadlines, we have tried to make the process as easy as possible for our customers. Under my management, we have improved our software design tools and website purchasing experience. We have introduced a suite of free online tools, including downloadable software

called PCB Creator that can be used to design a board and place the order directly through the software. More recently, we introduced a tool called InstantDFM, which was the first tool to provide immediate design feedback, meaning a user can upload their design to InstantDFM which will produce a design for manufacturability report and identify any errors that require attention prior to manufacturing. We have really tried to give designers tools to help make them successful. Our customers represent various industries and geographic markets. Traditionally, a majority of our customer base has been located here in Silicon Valley but today we have a much more national presence. Our demographic also ranges from the student and hobbyist market to professional engineers at the large enterprise level.

The Bay Area is a very expensive region of the country for a company to operate. How does Bay Area Circuits offer competitive pricing given the high cost of operating? It is definitely a costly region to do business, but it’s also beneficial to be located in the manufacturing hub of Silicon Valley. We focus on technology to try and help lower our costs. We don’t try to compete with offshore manufacturing. Rather, we focus on improving our equipment and making significant investments in the manufacturing process. In the past 18 to 24 months,

INDUSTRY INTERVIEW

we have purchased machinery that has really helped increase our capabilities and reduce production cost. It goes even further than equipment though— process and people are key factors to being able to stay competitive and keep our pricing low. To be a manufacturer in North America, we need to utilize today’s available technologies and we have spent as much money on equipment as we have spent on automating the process. I don’t believe there is any company built like us; from the moment we receive a customer’s design data all the way to shipping the order, we have streamlined the process to make it as efficient and cost-competitive as possible.

Do you also offer the opportunity for customers with a 10,000-board run to work with Bay Area in more depth to make sure the order is good to go before going into production? Yes. Our larger enterprise customers have always represented a significant source of our revenue. A lot of the investment we have made to create tools and processes to assist with the design and purchase process for our online customers are also available to our enterprise customers and help ensure data accuracy prior to production. We also have an internal team of engineers and support staff that utilize the same tools to ensure our customers will receive product that meets their specific requirements. We’re very agile in the way we identify and implement opportunities to strengthen the overall system.

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What specific pieces of equipment has Bay Area Circuits invested in over the past year? Our recent equipment investments have been made with continuous improvement to the manufacturing process in mind which ultimately benefits our customers. Our investments increase our capabilities and quality while ensuring on-time delivery and controlling costs, all of which provides value to our customers. These equipment purchases started last year with the acquisition of an Orbotech Paragon-8000M laser-direct imaging unit. That one piece of machinery really expanded our capabilities and overall quality. At the end of last year, we added an Excellon 136L Intelli-Drill System, which is not only a camera system for inner-layer registration, but doubles as a regular drill with high-speed capabilities. We have to be very lean and flexible as a quick-turn manufacturer, so that piece of machinery has been amazing for us. When dealing with prototype manufacturing, every minute is important. This year we have added a Seica Rapid 270 Flying Probe Test System, which includes eight probes for high speed testing. But perhaps the acquisition with the potential to make the largest impact has been the Camtek Gryphon, a 3D Functional InkJet Technology system, for the application of solder mask and legend. We were selected to beta test this new technology and are now the first in North America to utilize this technology in a production environment.

It is really incredible to see this technology in action; it saves us several hours of process time compared to the traditional process, which is invaluable. In addition to equipment, we have also worked to broaden the number of services we offer including the addition of new surface finishes to our Plating department which helps reduce production cycle time and increase our overall efficiency and quick turn capabilities.

What do you think is the next game-changer for the PCB industry? Will it be in the equipment or requirements? We have our challenges as a PCB manufacturer in Silicon Valley. I believe the industry should continue to focus on developing new technologies that add value to the manufacturing process. As time goes on, the necessity of equipment has become more important, especially with more complex designs coming into play. We see designers pushing the limits of their designs, and we need to be able to keep up with that demand from our customers. That said, I donâ&#x20AC;&#x2122;t think there will be one technology or piece of equipment that will change the PCB industry â&#x20AC;&#x201C; to stay relevant, I believe you have to understand the needs of your customers and make investments to meet their demands. And for Bay Area Circuits specifically, we will continue to invest in automating the process to remove room for error at every step

INDUSTRY INTERVIEW

of the way. I think that is where some companies may be left behind—if you don’t adapt to new requirements, you will be phased out by the global trends.

What makes customers choose Bay Area Circuits versus buying from a competitor? It would be hard to find a manufacturer that cares as much about the customer as we do. Our investments show how serious we are about this. I believe that most, if not all, PCB customers should have a better buying experience from the quote

stage all the way to shipping. For someone that purchases anything online, let’s say from a company like Amazon—these companies have set the bar for the online buying experience. For Bay Area Circuits, I want the customer experience to be second-to-none, in line with the high standards of today’s online ordering experience. Whether it is an equipment purchase or a process change, we are always looking at how that change will make this process better for our customers.

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